??A20 Port Controller

来源：华拓科技网

1.19. Port Controller

1.19.1. Port Description

The chip has several ports for multi-functional input/out pins. They are shown below: Port A(PA): 18 input/output port Port B(PB): 24 input/output port Port C(PC): 25 input/output port Port D(PD): 28 input/output port Port E(PE) : 12 input/output port Port F(PF) : 6 input/output port Port G(PG) : 12 input/output port Port H(PH) : 28 input/output port Port I(PI) : 22 input/output port

Port S(PS) : 84 input/output port for DRAM controller

For various system configurations, these ports can be easily configured by software. All these ports (except PS) can be configured as GPIO if multiplexed functions not used. 32 external PIO interrupt sources are supported and interrupt mode can be configured by software.

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1.19.2. Port Configuration Table

Port A(PA) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 Multiplex Function Select ERXD3 ERXD2 ERXD1 ERXD0 ETXD3 ETXD2 ETXD1 ETXD0 ERXCK ERXERR ERXDV EMDC EMDIO ETXEN ETXCK ECRS ECOL SPI1_CS0 SPI1_CLK SPI1_MOSI SPI1_MISO SPI1_CS1 SPI3_CS0 SPI3_CLK SPI3_MOSI SPI3_MISO SPI3_CS1 de UART1_TX UART1_RX UART6_TX UART1_RTS UART1_CTS UART1_DTR UART1_DSR UART1_DCD UART1_RING UART6_RX UART7_TX UART7_RX CAN_TX CAN_RX nfiETXERR Multiplex Function Select TWI0_SCK TWI0_SDA PWM0 Co

Port B(PB) PB0 PB1 PB2 PB3 PB4 PB5

Port A(PA) Multiplex Function Select Table

ntialUART2_RTS UART2_CTS UART2_TX GRXD3 GRXD2 GRXD1 GRXD0 GTXD3 GTXD2 GTXD1 GTXD0 UART2_RX GRXCK GNULL/ERXERR I2S1_MCLK GRXCTL/RXDV GMDC GMDIO GTXCTL/ETXEN GNULL/ETXCK I2S1_BCLK GTXCK/ECRS GCLKIN/ECOL I2S1_LRCK I2S1_DO GNULL/ETXERR I2S1_DI STANBYWFI SPDIF_MCLK

Port B(PB) PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 Multiplex Function Select I2S_BCLK I2S_LRCK I2S_DO0 I2S_DO1 I2S_DO2 I2S_DO3 I2S_DI SPI2_CS1 SPI2_CS0 SPI2_CLK SPI2_MOSI SPI2_MISO TWI1_SCK TWI1_SDA TWI2_SCK TWI2_SDA AC97_BCLK AC97_SYNC AC97_DO AC97_DI JTAG_MS0 JTAG_CK0 JTAG_DO0 JTAG_DI0 UART0_TX

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10

Port C(PC) nfiMultiplex Function Select NWE# NALE SPI0_MOSI SPI0_MISO SPI0_CLK NCLE NCE1 NCE0 NRE# NRB0 NRB1 UART0_RX de IR1_TX IR1_RX Port B(PB) Multiplex Function Select Table

Co NDQ0 NDQ1 NDQ2

ntialSPDIF_DI SPDIF_DO

Port C(PC) PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 Multiplex Function Select NDQ3 NDQ4 NDQ5 NDQ6 NDQ7 NWP NCE2 NCE3 NCE4 NCE5 NCE6 NCE7 SDC2_D3 SPI2_CS0 SPI2_CLK SPI2_MOSI SPI2_MISO SPI0_CS0 NDQS de LVDS0_VP0 Port C(PC) Multiplex Function Select Table

Port D(PD) PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 Multiplex Function Select LCD0_D0 LCD0_D1 LCD0_D2 LCD0_D3 LCD0_D4 LCD0_D5 LCD0_D6 LCD0_D7 LCD0_D8 LCD0_D9 nfiLVDS0_VN0 LVDS0_VP1 LVDS0_VN1 LVDS0_VP2 LVDS0_VN2 CoPD10 PD11 PD12 PD13 PD14

LVDS0_VPC LVDS0_VNC LVDS0_VP3 LVDS0_VN3 LVDS1_VP0 LVDS1_VN0 LVDS1_VP1 LVDS1_VN1 LVDS1_VP2 LCD0_D10 LCD0_D11 LCD0_D12 LCD0_D13 LCD0_D14 A20 User Manual (Revision 1.0) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 243 / 835

ntialEINT12 EINT13 EINT14 EINT15

Port D(PD) PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 Multiplex Function Select LCD0_D15 LCD0_D16 LCD0_D17 LCD0_D18 LCD0_D19 LCD0_D20 LCD0_D21 LCD0_D22 LCD0_D23 LCD0_CLK LCD0_DE LVDS1_VN2 LVDS1_VPC LVDS1_VNC LVDS1_VP3 LVDS1_VN3 CSI1_MCLK SMC_VPPEN SMC_VPPPP SMC_DET SMC_VCCEN SMC_RST LCD0_HSYNC SMC_SLK

Port E(PE) PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 Multiplex Function Select TS0_CLK deCSI0_PCLK LCD0_VSYNC SMC_SDA Port D(PD) Multiplex Function Select Table

nfiTS0_SYNC TS0_DLVD TS0_D0 TS0_D1 TS0_D2 TS0_D3 TS0_D4 TS0_D5 TS0_D6 TS0_D7 CSI0_HSYNC CSI0_VSYNC CSI0_D0 CSI0_D1 CSI0_D2 CSI0_D3 CSI0_D4 CSI0_D5 CSI0_D6 CSI0_D7 TS0_ERR CSI0_MCLK CoPE10 PE11 Port E(PE) Multiplex Function Select Table

Port F(PF) PF0

ntial JTAG_MS1

Port F(PF) PF1 PF2 PF3 PF4 PF5 Multiplex Function Select SDC0_D0 SDC0_CLK SDC0_CMD SDC0_D3 SDC0_D2 JTAG_DI1 UART0_TX JTAG_DO1 UART0_RX JTAG_CK1 Port F(PF) Multiplex Function Select Table

Port G(PG) PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PG10 PG11 TS1_CLK TS1_ERR TS1_SYNC TS1_DVLD TS1_D0 TS1_D1 TS1_D2 TS1_D3 TS1_D4 TS1_D5 TS1_D6 TS1_D7 Multiplex Function Select CSI1_PCLK CSI1_MLCK CSI1_HSYNC SDC1_D0 CSI1_VSYNC SDC1_D1 CSI1_D0 CSI1_D1 CSI1_D2 CSI1_D3 CSI1_D4 CSI1_D5 CSI1_D6 CSI1_D7 SDC1_D2 SDC1_D3 deUART4_TX UART4_RX nfiLCD1_D0 LCD1_D1 LCD1_D2 LCD1_D3 LCD1_D4 LCD1_D5 LCD1_D6 Port G(PG) Multiplex Function Select Table

Port Multiplex Function Select H(PH) CoPH0 PH1 PH2 PH3 PH4 PH5 PH6

ntialSDC1_CMD SDC1_CLK CSI0_D8 CSI0_D9 UART3_TX CSI0_D10 UART3_RX CSI0_D11 UART3_RTS CSI0_D12 UART3_CTS CSI0_D13 CSI0_D14 CSI0_D15 EINT0 EINT1 EINT2 EINT3 EINT4 EINT5 EINT6 CSI1_D0 CSI1_D1 CSI1_D2 CSI1_D3 CSI1_D4 CSI1_D5 CSI1_D6

Port Multiplex Function Select H(PH) PH7 PH8 PH9 PH10 PH11 PH12 PH13 PH14 PH15 PH16 PH17 PH18 PH19 PH20 PH21 PH22 PH23 PH24 PH25 PH26 PH27 LCD1_D7 LCD1_D8 LCD1_D9 LCD1_D10 LCD1_D11 LCD1_D12 LCD1_D13 LCD1_D14 LCD1_D15 LCD1_D16 LCD1_D17 LCD1_D18 LCD1_D19 LCD1_D20 LCD1_D21 LCD1_D22 LCD1_D23 ERXD3 ERXD2 ERXD1 ERXD0 UART5_RX MS_CLK KP_IN0 KP_IN1 KP_IN2 KP_IN3 MS_D0 MS_D1 MS_D2 MS_D3 EINT7 EINT8 EINT9 EINT10 EINT11 EINT12 EINT13 CSI1_D7 CSI1_D8 CSI1_D9 ETXD3 ETXD2 ETXD1 ETXD0 ERXCK PS2_SCK1 PS2_SDA1 KP_IN4 KP_IN5 KP_IN6 KP_IN7 KP_OUT0 ERXERR KP_OUT1 ERXDV EMDC CAN_TX deSMC_SDA CAN_RX KP_OUT2 KP_OUT3 KP_OUT4 KP_OUT5 KP_OUT6 SDC1_CLK SDC1_D0 SDC1_D1 SDC1_D2 SDC1_D3 TWI3_SCK TWI3_SDA TWI4_SCK TWI4_SDA EMDIO nfiLCD1_CLK LCD1_DE ETXCK ECRS ECOL LCD1_HSYNC LCD1_VSYNC ETXERR KP_OUT7 Multiplex Function Select ETXEN Co

Port I(PI) PI0 PI1 PI2 PI3 PI4 PI5

Port H(PH) Multiplex Function Select Table

ntialCSI1_D10 CSI1_D11 CSI1_D12 CSI1_D13 CSI1_D14 CSI1_D15 CSI1_D16 CSI1_D17 CSI1_D18 CSI1_D19 CSI1_D20 CSI1_D21 CSI1_D22 CSI1_D23 CSI1_PCLK CSI1_FIELD CSI1_HSYNC CSI1_VSYNC SMC_RST SMC_VPPEN EINT14 SMC_VPPPP EINT15 SMC_DET EINT16 SMC_VCCEN EINT17 SMC_SLK EINT18 EINT19 EINT20 EINT21 SDC1_CMD

Port I(PI) PI6 PI7 PI18 PI19 PI10 PI11 PI12 PI13 PI14 PI15 PI16 PI17 PI18 PI19 PI20 PI21 Multiplex Function Select SDC3_D0 SDC3_D1 SDC3_D2 SDC3_D3 SPI0_CS0 SPI0_CLK SPI0_MOSI SPI0_MISO SPI0_CS1 SPI1_CS1 SPI1_CS0 SPI1_CLK SPI1_MOSI SPI1_MISO PS2_SCK0 PS2_SDA0 UART5_TX EINT22 EINT23 EINT24 EINT25 EINT26 EINT27 EINT28 EINT29 EINT30 EINT31 UART5_RX UART6_TX UART6_RX PS2_SCK1 PS2_SDA1 UART2_RTS UART2_CTS UART2_TX

1.19.3. Port Register List

CoModule Name PIO

nfiBase Address 0x01C20800 Offset n*0x24+0x00 n*0x24+0x04 n*0x24+0x08 n*0x24+0x0C Description Port n Configure Register 0 (n from 0 to 9) Port n Configure Register 1 (n from 0 to 9) Port n Configure Register 2 (n from 0 to 9) Port n Configure Register 3 (n from 0 to 9) deUART2_RX UART7_TX UART7_RX Port I(PI) Multiplex Function Select Table

ntialCLK_OUT_A CLK_OUT_B TCLKIN0 TCLKIN1 HSCL HSDA

Register Name Pn_DAT Pn_DRV0 Pn_DRV1 Pn_PUL0 Pn_PUL1 PIO_INT_CFG0 PIO_INT_CFG1 PIO_INT_CFG2 PIO_INT_CFG3 PIO_INT_CTL PIO_INT_STA PIO_INT_DEB Offset n*0x24+0x10 n*0x24+0x14 n*0x24+0x18 n*0x24+0x1C n*0x24+0x20 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 Description Port n Data Register (n from 0 to 9) Port n Multi-Driving Register 0 (n from 0 to 9) Port n Multi-Driving Register 1 (n from 0 to 9) Port n Pull Register 0 (n from 0 to 9) Port n Pull Register 1 (n from 0 to 9) PIO Interrrupt Configure Register 0 PIO Interrrupt Configure Register 1 PIO Interrrupt Configure Register 2 PIO Interrrupt Configure Register 3 PIO Interrupt Control Register PIO Interrupt Status Register

1.19.4. Port Register Description

1.19.4.1.

PA CONFIGURE REGISTER 0

Offset: 0x00 Bit 31 Co30:28 R/W 0 27 / / 26:24 R/W 0

nfiRead/Write / Default Description / / PA7_SELECT 000: Input 010: ETXD0 100: Reserved 110: Reserved Reserved PA6_SELECT 000: Input 010: ETXD1 deRegister Name: PA_CFG0 Default Value: 0x0000_0000 001: Output 011: SPI3_MOSI 101: GTXD0 111: Reserved 001: Output 011: SPI3_CLK A20 User Manual (Revision 1.0) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 248 / 835

ntialPIO Interrupt Debounce Register

Offset: 0x00 Bit Read/Write Register Name: PA_CFG0 Default Value: 0x0000_0000 Default Description 100: Reserved 110: Reserved 101: GTXD1 111: Reserved 23 / / / PA5_SELECT 000: Input 22:20 R/W 0 010: ETXD2 100: Reserved 110: Reserved 19 / / / PA4_SELECT 000: Input 18:16 R/W 0 010: ETXD3 15 / / nfi100: UART2_RX 110: Reserved / / / PA2_SELECT 000: Input 010:ERXD1 R/W 0 100: UART2_TX 110: Reserved / PA1_SELECT 000: Input 010: ERXD2 / / R/W 0 100: UART2_CTS 110: Reserved Reserved / / 14:12 R/W 0 11 Co7 6:4 3

ntial 001: Output 011: SPI3_CS0 101: GTXD2 111: Reserved 001: Output 011: SPI1_CS1 101: GTXD3 111: Reserved 001: Output 011: SPI1_MISO 101: GRXD0 111: Reserved 001: Output 011: SPI1_MOSI 101: GRXD1 111: Reserved 001: Output 011: SPI1_CLK 101: GRXD2 111: Reserved

Offset: 0x00 Bit Read/Write Register Name: PA_CFG0 Default Value: 0x0000_0000 Default Description PA0_SELECT 000: Input 001: Output 2:0 R/W 0 010: ERXD3 100: UART2_RTS 110: Reserved 1.19.4.2.

PA CONFIGURE REGISTER 1

Offset: 0x04 Bit 31 Read/Write / Register Name: PA_CFG1 Default Description / / Default Value: 0x0000_0000 30:28 R/W 0 nfi110: I2S1_LRCK / / / PA14_SELECT 000: Input 010:ETXCK R/W 0 100: UART1_DTR 110: I2S1_BCLK / PA13_SELECT 000: Input 010:ETXEN / / R/W 0 100: UART1_CTS 110: Reserved / PA12_SELECT 000: Input / / R/W 0 27 26:24 Co23 22:20 19 18:16

dePA15_SELECT 000: Input 010: ECRS 100: UART1_DSR ntial011: SPI1_CS0 101: GRXD3 111: Reserved 001: Output 011: UART7_RX 101: GTXCK/ECRS 111: Reserved 001: Output 011: UART7_TX 101: GNULL/ETXCK 111: Reserved 001: Output 011: UART6_RX 101: GTXCTL/ETXEN 111: Reserved 001: Output

Offset: 0x04 Bit Read/Write Register Name: PA_CFG1 Default Value: 0x0000_0000 Default Description 010:EMDIO 011: UART6_TX 101: GMDIO 111: Reserved 100: UART1_RTS 110: Reserved 15 / / / PA11_SELECT 000: Input 14:12 R/W 0 010: EMDC 100: UART1_RX 110: Reserved 11 / / / PA10_SELECT 000: Input 10:8 R/W 0 010:ERXDV 7 / / nfiR/W 0 010: ERXERR 100: Reserved 110: I2S1_MCLK / / / PA8_SELECT 000: Input 010:ERXCK R/W 0 100: Reserved 110: Reserved de 100: UART1_TX 110: Reserved / PA9_SELECT 000: Input Register Name: PA_CFG2 Default Value: 0x0000_0000 6:4 3 Co2:0

1.19.4.3. PA CONFIGURE REGISTER 2

Offset: 0x08

ntial 001: Output 011: Reserved 101: GMDC 111: Reserved 001: Output 011: Reserved 101: GRXCTL/ERXDV 111: Reserved 001: Output 011: SPI3_CS1 101: GNULL/ERXERR 111: Reserved 001: Output 011: SPI3_MISO 101: GRXCK 111: Reserved

Bit 31:7 Read/Write / Default Description / / PA17_SELECT 000: Input 001: Output 011: CAN_RX 101: GNULL/ETXERR 111: Reserved 100: UART1_RING 110: I2S1_DI 3 / / / PA16_SELECT 000: Input 2:0 R/W 0 010: ECOL 100: UART1_DCD 110: I2S1_DO 1.19.4.4.

PA CONFIGURE REGISTER 3

Offset: 0x0C Bit 31:0 Read/Write / Default Description / / 1.19.4.5.

CoBit Read/Write / 31:18 / 17:0 R/W 0 Offset: 0x10

nfiPA DATA REGISTER

Default Description / PA_DAT deRegister Name: PA_CFG3 Default Value: 0x0000_0000 Register Name: PA_DAT Default Value: 0x0000_0000 If the port is configured as input, the corresponding bit is the pin state. If the port is configured as output, the pin state is the same as the corresponding bit. The read bit value is the value setup by software. If the port is configured as functional pin, the undefined value will be read. ntial 001: Output 011: CAN_TX 101: GCLKIN/ECOL 111: Reserved 6:4 R/W 0 010: ETXERR

1.19.4.6. PA MULTI-DRIVING REGISTER 0

Register Name: PA_DRV0 Default Value: 0x5555_5555 Default Description PA_DRV PA[n] Multi-Driving Select (n = 0~15) 00: Level 0 10: Level 2 Offset: 0x14 Bit [2i+1:2i] (i=0~15) Read/Write R/W 0x1 1.19.4.7.

PA MULTI-DRIVING REGISTER 1

Offset: 0x18 Bit 31:4 [2i+1:2i] (i=0~1) Read/Write / Register Name: PA_DRV1 Default Description / / Default Value: 0x0000_0005 R/W 1.19.4.8.

Offset: 0x1C Bit CoRead/Write [2i+1:2i] (i=0~15) R/W 0x0 nfiPA PULL REGISTER 0

Default Description PA_PULL 10: Pull-down

dePA_DRV 0x1 00: Level 0 10: Level 2 Register Name: PA_PULL0 Default Value: 0x0000_0000 PA[n] Multi-Driving Select (n = 16~17) 01: Level 1 11: Level 3 PA[n] Pull-up/down Select (n = 0~15) 00: Pull-up/down disable 01: Pull-up 11: Reserved ntial01: Level 1 11: Level 3

1.19.4.9. PA PULL REGISTER 1

Register Name: PA_PULL1 Default Value: 0x0000_0000 Default Description / / Offset: 0x20 Bit 31:4 [2i+1:2i] (i=0~1) Read/Write / PA_PULL R/W 0x0 PA[n] Pull-up/down Select (n = 16~17) 10: Pull-down 00: Pull-up/down disable 01: Pull-up enable 11: Reserved

1.19.4.10. PB CONFIGURE REGISTER 0

Offset: 0x24 Bit 31 Read/Write / Register Name: PB_CFG0 Default Description / / nfi100: Reserved 110: Reserved / / / PB6_SELECT 000: Input R/W 0 010: I2S_BCLK 100: Reserved 110: Reserved / PB5_SELECT 000: Input / / R/W 0 010: I2S_MCLK 100: Reserved 110: Reserved / / / 30:28 R/W 0 deDefault Value: 0x0000_0000 PB7_SELECT 000: Input 010: I2S_LRCK 27 Co23 22:20 19

ntial001: Output 011: AC97_SYNC 101: Reserved 111: Reserved 001: Output 011: AC97_BCLK 101: Reserved 111: Reserved 001: Output 011: AC97_MCLK 101: Reserved 111: Reserved

Offset: 0x24 Bit Read/Write Register Name: PB_CFG0 Default Value: 0x0000_0000 Default Description PB4_SELECT 000: Input 001: Output 18:16 R/W 0 010: IR0_RX 100: Reserved 110: Reserved 15 / / / PB3_SELECT 000: Input 14:12 R/W 0 010: IR0_TX 100: SPDIF_MCLK 11 / / / 110: STANBYWFI 10:8 R/W 0 dePB2_SELECT 000: Input 010: PWM0 100: Reserved 110: Reserved / PB1_SELECT 000: Input 010: TWI0_SDA 100: Reserved 110: Reserved / PB0_SELECT 000: Input 010: TWI0_SCK 100: Reserved 110: Reserved nfiR/W 0 / / R/W 0 7 / / 6:4 3 Co2:0

ntial 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved

1.19.4.11. PB CONFIGURE REGISTER 1

Offset: 0x28 Bit 31 Read/Write / Register Name: PB_CFG1 Default Value: 0x0000_0000 Default Description / / PB15_SELECT 000: Input 30:28 R/W 0 010: SPI2_CLK 100: Reserved 110: Reserved 27 / / / PB14_SELECT 000: Input 26:24 R/W 0 010: SPI2_CS0 100: Reserved 110: Reserved / de PB13_SELECT 000: Input 010: SPI2_CS1 100: SPDIF_DO 110: Reserved / PB12_SELECT 000: Input 010: I2S_DI 100: SPDIF_DI 110: Reserved / PB11_SELECT 000: Input 010: I2S_DO3 100: Reserved 110: Reserved / PB10_SELECT 23 / / nfi/ / R/W 0 / / R/W 0 / R/W / 0 22:20 R/W 0 19 18:16 Co15 14:12 11 10:8

ntial 001: Output 011: JTAG_CK0 101: Reserved 111: Reserved 001: Output 011: JTAG_MS0 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: AC97_DI 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved

Offset: 0x28 Bit Read/Write Register Name: PB_CFG1 Default Value: 0x0000_0000 Default Description 000: Input 010: I2S_DO2 001: Output 011: Reserved 101: Reserved 111: Reserved 100: Reserved 110: Reserved 7 / / / PB9_SELECT 000: Input 6:4 R/W 0 010: I2S_DO1 100: Reserved 110: Reserved 3 / / / PB8_SELECT 000: Input 2:0 R/W 0 010: I2S_DO0 de 100: Reserved 110: Reserved Register Name: PB_CFG2 Default Value: 0x0000_0000 / PB23_SELECT 000: Input 010: UART0_RX 100: Reserved 110: Reserved / PB22_SELECT 000: Input 010: UART0_TX 1.19.4.12. PB CONFIGURE REGISTER 2

Offset: 0x2C Bit 31 Co30:28 R/W 0 27 / / 26:24 R/W 0

nfiRead/Write / Default Description /

ntial 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: AC97_DO 101: Reserved 111: Reserved 001: Output 011: IR1_RX 101: Reserved 111: Reserved 001: Output 011: IR1_TX

Offset: 0x2C Bit Read/Write Register Name: PB_CFG2 Default Value: 0x0000_0000 Default Description 100: Reserved 110: Reserved 101: Reserved 111: Reserved 23 / / Reserved PB21_SELECT 000: Input 22:20 R/W 0 010: TWI2_SDA 100: Reserved 110: Reserved 19 / / / PB20_SELECT 000: Input 18:16 R/W 0 010: TWI2_SCK 100: Reserved 110: Reserved / de PB19_SELECT 000: Input 010: TWI1_SDA 100: Reserved 110: Reserved / PB18_SELECT 000: Input 010: TWI1_SCK 100: Reserved 110: Reserved / PB17_SELECT 000: Input 010: SPI2_MISO 100: Reserved 110: Reserved / 15 / / nfi/ / R/W 0 / / R/W 0 / / 14:12 R/W 0 11 Co7 6:4 3

ntial 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: JTAG_DI0 101: Reserved 111: Reserved

Offset: 0x2C Bit Read/Write Register Name: PB_CFG2 Default Value: 0x0000_0000 Default Description PB16_SELECT 000: Input 001: Output 2:0 R/W 0 010: SPI2_MOSI 100: Reserved 110: Reserved

1.19.4.13. PB CONFIGURE REGISTER 3

Offset: 0x30 Bit 31:0 Read/Write / Register Name: PB_CFG3 Default Description / / Default Value: 0x0000_0000

1.19.4.14. PB DATA REGISTER

Offset: 0x34 Bit 31:24 Co23:0 R/W 0

1.19.4.15. PB MULTI-DRIVING REGISTER 0

Offset: 0x38 Register Name: PB_DRV0 Default Value: 0x5555_5555

nfiRead/Write / Default Description / / PB_DAT deRegister Name: PB_DAT Default Value: 0x0000_0000 If the port is configured as input, the corresponding bit is the pin state. If the port is configured as output, the pin state is the same as the corresponding bit. The read bit value is the value setup by software. If the port is configured as functional pin, the undefined value will be read. ntial011: JTAG_DO0 101: Reserved 111: Reserved

Bit [2i+1:2i] (i=0~15) Read/Write Default Description PB_DRV PB[n] Multi-Driving Select (n = 0~15) 00: Level 0 10: Level 2 01: Level 1 11: Level 3 R/W 0x1

1.19.4.16. PB MULTI-DRIVING REGISTER 1

Offset: 0x3C Bit 31:16 [2i+1:2i] (i=0~7) Read/Write / Register Name: PB_DRV1 Default Description / / Default Value: 0x0000_5555 PB_DRV R/W 0x1

Offset: 0x40 Bit [2i+1:2i] Co(i=0~15) nfiRead/Write Default Description PB_PULL R/W 0x0 10: Pull-down Read/Write Default Description 1.19.4.17. PB PULL REGISTER 0

1.19.4.18. PB PULL REGISTER 1

Offset: 0x44 Bit

de00: Level 0 10: Level 2 Register Name: PB_PULL0 Default Value: 0x0000_0000 Register Name: PB_PULL1 Default Value: 0x0000_0000 PB[n] Multi-Driving Select (n = 16~23) 01: Level 1 11: Level 3 PB[n] Pull-up/down Select (n = 0~15) 00: Pull-up/down disable 01: Pull-up 11: Reserved ntial

Offset: 0x44 Bit 31:16 [2i+1:2i] (i=0~7) Read/Write / Register Name: PB_PULL1 Default Value: 0x0000_0000 Default Description / / PB[n] Pull-up/down Select (n = 16~23) 10: Pull-down R/W 0x0 00: Pull-up/down disable 01: Pull-up enable 11: Reserved

1.19.4.19. PC CONFIGURE REGISTER 0

Offset: 0x48 Bit 31 Read/Write / Register Name: PC_CFG0 Default Description / / Default Value: 0x0000_0000 30:28 R/W 0 dePC7_SELECT 000: Input 010: NRB1 100: Reserved 110: Reserved / PC6_SELECT 000: Input 010: NRB0 100: Reserved 110: Reserved / PC5_SELECT 000: Input 010: NRE# 100: Reserved 110: Reserved / PC4_SELECT 000: Input nfi/ / R/W 0 / / R/W 0 / R/W / 0 27 26:24 Co23 22:20 19 18:16

ntial001: Output 011: SDC2_CLK 101: Reserved 111: Reserved 001: Output 011: SDC2_CMD 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output PB_PULL

Offset: 0x48 Bit Read/Write Register Name: PC_CFG0 Default Value: 0x0000_0000 Default Description 010: NCE0 011: Reserved 101: Reserved 111: Reserved 100: Reserved 110: Reserved 15 / / / PC3_SELECT 000: Input 14:12 R/W 0 010: NCE1 100: Reserved 110: Reserved 11 / / / PC2_SELECT 000: Input 10:8 R/W 0 010: NCLE de 100: Reserved 110: Reserved / PC1_SELECT 000: Input 010: NALE 100: Reserved 110: Reserved / PC0_SELECT 000: Input 010: NWE 100: Reserved 110: Reserved Register Name: PC_CFG1 Default Value: 0x0000_0000 7 / / nfiR/W 0 / / R/W 0 6:4 3 Co2:0

1.19.4.20. PC CONFIGURE REGISTER 1

Offset: 0x4C

ntial 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: SPI0_CLK 101: Reserved 111: Reserved 001: Output 011: SPI0_MISO 101: Reserved 111: Reserved 001: Output 011: SPI0_MOSI 101: Reserved 111: Reserved

Bit 31 Read/Write / Default Description / / PC15_SELECT 000: Input 001: Output 011: Reserved 101: Reserved 111: Reserved 100: Reserved 110: Reserved 27 / / / PC14_SELECT 000: Input 26:24 R/W 0 010: NDQ6 100: Reserved 110: Reserved 23 / / / 22:20 R/W 0 de000: Input 010: NDQ5 100: Reserved 110: Reserved / PC12_SELECT 000: Input 010: NDQ4 100: Reserved 110: Reserved / PC11_SELECT 000: Input 010: NDQ3 100: Reserved 110: Reserved / PC10_SELECT 000: Input 010: NDQ2 100: Reserved PC13_SELECT 19 / / nfiR/W 0 / / R/W 0 / / R/W 0 18:16 15 Co14:12 11 10:8

ntial 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: SDC2_D3 101: Reserved 111: Reserved 001: Output 011: SDC2_D2 101: Reserved 30:28 R/W 0 010: NDQ7

Offset: 0x4C Bit 7 Read/Write / Register Name: PC_CFG1 Default Value: 0x0000_0000 Default Description 110: Reserved / / 111: Reserved PC9_SELECT 000: Input 6:4 R/W 0 010: NDQ1 100: Reserved 110: Reserved 3 / / / PC8_SELECT 000: Input 2:0 R/W 0 010: NDQ0 100: Reserved 110: Reserved de Register Name: PC_CFG2 Default Value: 0x0000_0000 / PC23_SELECT 000: Input 010: Reserved 100: Reserved 110: Reserved / PC22_SELECT 000: Input 010: NCE7 100: Reserved 110: Reserved /

1.19.4.21. PC CONFIGURE REGISTER 2

Offset: 0x50 Bit 31 nfiRead/Write / Default Description / R/W 0 / / R/W 0 / / Co17 26:24 23

ntial 001: Output 011: SDC2_D1 101: Reserved 111: Reserved 001: Output 011: SDC2_D0 101: Reserved 111: Reserved 001: Output 011: SPI0_CS0 101: Reserved 111: Reserved 001: Output 011: SPI2_MISO 101: Reserved 111: Reserved

Offset: 0x50 Bit Read/Write Register Name: PC_CFG2 Default Value: 0x0000_0000 Default Description PC21_SELECT 000: Input 001: Output 22:20 R/W 0 010: NCE6 100: Reserved 110: Reserved 19 / / / PC20_SELECT 000: Input 18:16 R/W 0 010: NCE5 100: Reserved 110: Reserved 15 / / / 14:12 R/W 0 dePC19_SELECT 000: Input 010: NCE4 100: Reserved 110: Reserved / PC18_SELECT 000: Input 010: NCE3 100: Reserved 110: Reserved / PC17_SELECT 000: Input 010: NCE2 100: Reserved 110: Reserved / PC16_SELECT 000: Input 010: NWP nfiR/W 0 / / R/W 0 / / R/W 0 11 / / 10:8 7 Co6:4 3 2:0

ntial011: SPI2_MOSI 101: Reserved 111: Reserved 001: Output 011: SPI2_CLK 101: Reserved 111: Reserved 001: Output 011: SPI2_CS0 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved

Offset: 0x50 Bit Read/Write Register Name: PC_CFG2 Default Value: 0x0000_0000 Default Description 100: Reserved 110: Reserved 101: Reserved 111: Reserved

1.19.4.22. PC CONFIGURE REGISTER 3

Offset: 0x54 Bit 31:3 Read/Write / Register Name: PC_CFG3 Default Description / / Default Value: 0x0000_0000 PC24_SELECT 000: Input 010: NDQS 2:0 R/W 0 de 100: Reserved 110: Reserved Register Name: PC_DAT Default Value: 0x0000_0000 / PC_DAT

1.19.4.23. PC DATA REGISTER

Offset: 0x58 Bit 31:24 Co23:0 R/W 0

nfiRead/Write / Default Description / If the port is configured as input, the corresponding bit is the pin state. If the port is configured as output, the pin state is the same as the corresponding bit. The read bit value is the value setup by software. If the port is configured as functional pin, the undefined value will be read. ntial 001: Output 011: Reserved 101: Reserved 111: Reserved

1.19.4.24. PC MULTI-DRIVING REGISTER 0

Offset: 0x5C Bit [2i+1:2i] (i=0~15) Read/Write Register Name: PC_DRV0 Default Value: 0x5555_5555 Default Description PC_DRV R/W 0x1 PC[n] Multi-Driving_SELECT (n = 0~15) 00: Level 0 10: Level 2 01: Level 1 11: Level 3

1.19.4.25. PC MULTI-DRIVING REGISTER 1

Offset: 0x60 Bit 31:18 [2i+1:2i] (i=0~8) Read/Write / Register Name: PC_DRV1 Default Description / / Default Value: 0x0001_5555 R/W

1.19.4.26. PC PULL REGISTER 0

Offset: 0x Bit CoRead/Write Default [2i+1:2i] (i=0~15) R/W nfiDescription PC_PULL 0x0000_5140 dePC_DRV 0x1 00: Level 0 10: Level 2 10: Pull-down PC[n] Multi-Driving Select (n = 16~24) 01: Level 1 11: Level 3

ntialRegister Name: PC_PULL0 Default Value: 0x0000_5140 PC[n] Pull-up/down Select (n = 0~15) 00: Pull-up/down disable 01: Pull-up 11: Reserved

1.19.4.27. PC PULL REGISTER 1

Offset: 0x68 Bit 31:18 [2i+1:2i] (i=0~8) Read/Write / Default / Register Name: PC_PULL1 Default Value: 0x0000_4016 Description R/W 0x0000_4016

1.19.4.28. PD CONFIGURE REGISTER 0

Offset: 0x6C Bit 31 Read/Write / Register Name: PD_CFG0 Default Description / / nfi100: Reserved 110: Reserved Reserved / / PD6_SELECT 000: Input R/W 0 010: LCD0_D6 100: Reserved 110: Reserved / PD5_SELECT 000: Input / / R/W 0 010: LCD0_D5 100: Reserved 110: Reserved / / / 30:28 R/W 0 deDefault Value: 0x0000_0000 PD7_SELECT 000: Input 010: LCD0_D7 27 Co23 22:20 19

ntial/ PC_PULL PC[n] Pull-up/down Select (n = 16~24) 00: Pull-up/down disable 01: Pull-up 10: Pull-down 11: Reserved 001: Output 011: LVDS0_VNC 101: Reserved 111: Reserved 001: Output 011: LVDS0_VPC 101: Reserved 111: Reserved 001: Output 011: LVDS0_VN2 101: Reserved 111: Reserved

Offset: 0x6C Bit Read/Write Register Name: PD_CFG0 Default Value: 0x0000_0000 Default Description PD4_SELECT 000: Input 001: Output 18:16 R/W 0 010: LCD0_D4 100: Reserved 110: Reserved 15 / / / PD3_SELECT 000: Input 14:12 R/W 0 010: LCD0_D3 100: Reserved 110: Reserved 11 / / / 10:8 R/W 0 dePD2_SELECT 000: Input 010: LCD0_D2 100: Reserved 110: Reserved / PD1_SELECT 000: Input 010: LCD0_D1 100: Reserved 110: Reserved / PD0_SELECT 000: Input 010: LCD0_D0 100: Reserved 110: Reserved nfiR/W 0 / / R/W 0 7 / / 6:4 3 Co2:0

ntial011: LVDS0_VP2 101: Reserved 111: Reserved 001: Output 011: LVDS0_VN1 101: Reserved 111: Reserved 001: Output 011: LVDS0_VP1 101: Reserved 111: Reserved 001: Output 011: LVDS0_VN0 101: Reserved 111: Reserved 001: Output 011: LVDS0_VP0 101: Reserved 111: Reserved

1.19.4.29. PD CONFIGURE REGISTER 1

Offset: 0x70 Bit 31 Read/Write / Register Name: PD_CFG1 Default Value: 0x0000_0000 Default Description / / PD15_SELECT 000: Input 30:28 R/W 0 010: LCD0_D15 100: Reserved 110: Reserved 27 / / / PD14_SELECT 000: Input 26:24 R/W 0 010: LCD0_D14 100: Reserved 110: Reserved / de PD13_SELECT 000: Input 010: LCD0_D13 110: Reserved / 100: Reserved PD12_SELECT 000: Input 010: LCD0_D12 100: Reserved 110: Reserved / PD11_SELECT 000: Input 010: LCD0_D11 100: Reserved 110: Reserved / PD10_SELECT 23 / / nfi/ / R/W 0 / / R/W 0 / R/W / 0 22:20 R/W 0 19 18:16 Co15 14:12 11 10:8

ntial 001: Output 011: LVDS1_VN2 101: Reserved 111: Reserved 001: Output 011: LVDS1_VP2 101: Reserved 111: Reserved 001: Output 011: LVDS1_VN1 101: Reserved 111: Reserved 001: Output 011: LVDS1_VP1 101: Reserved 111: Reserved 001: Output 011: LVDS1_VN0 101: Reserved 111: Reserved

Offset: 0x70 Bit Read/Write Register Name: PD_CFG1 Default Value: 0x0000_0000 Default Description 000: Input 001: Output 011: LVDS1_VP0 101: Reserved 111: Reserved 010: LCD0_D10 100: Reserved 110: Reserved 7 / / / PD9_SELECT 000: Input 6:4 R/W 0 010: LCD0_D9 100: Reserved 110: Reserved 3 / / / PD8_SELECT 000: Input 2:0 R/W 0 de 010: LCD0_D8 100: Reserved 110: Reserved Register Name: PD_CFG2 Default Value: 0x0000_0000 / PD23_SELECT 000: Input 010: LCD0_D23 100: Reserved 110: Reserved / PD22_SELECT 000: Input 010: LCD0_D22 1.19.4.30. PD CONFIGURE REGISTER 2

Offset: 0x74 Bit 31 Co30:28 R/W 0 27 / / 26:24 R/W 0

nfiRead/Write / Default Description /

ntial 001: Output 011: LVDS0_VN3 101: Reserved 111: Reserved 001: Output 011: LVDS0_VP3 101: Reserved 111: Reserved 001: Output 011: SMC_DET 101: Reserved 111: Reserved 001: Output 011: SMC_VPPPP

Offset: 0x74 Bit Read/Write Register Name: PD_CFG2 Default Value: 0x0000_0000 Default Description 100: Reserved 110: Reserved 101: Reserved 111: Reserved 23 / / / PD21_SELECT 000: Input 22:20 R/W 0 010: LCD0_D21 100: Reserved 110: Reserved 19 / / / PD20_SELECT 000: Input 18:16 R/W 0 010: LCD0_D20 100: Reserved 110: Reserved / 15 / / nfi100: Reserved 110: Reserved / / / PD18_SELECT 000: Input R/W 0 010: LCD0_D18 100: Reserved 110: Reserved / PD17_SELECT 000: Input / / R/W 0 010: LCD0_D17 100: Reserved 110: Reserved / / / 14:12 R/W 0 11 Co7 6:4 3

ntial 001: Output 011: SMC_VPPEN 101: Reserved 111: Reserved 001: Output 011: CSI1_MCLK 101: Reserved 111: Reserved 001: Output 011: LVDS1_VN3 101: Reserved 111: Reserved 001: Output 011: LVDS1_VP3 101: Reserved 111: Reserved 001: Output 011: LVDS1_VNC 101: Reserved 111: Reserved

Offset: 0x74 Bit Read/Write Register Name: PD_CFG2 Default Value: 0x0000_0000 Default Description PD16_SELECT 000: Input 001: Output 2:0 R/W 0 010: LCD0_D16 110: Reserved 100: Reserved

1.19.4.31. PD CONFIGURE REGISTER 3

Offset: 0x78 Bit 31:15 Read/Write / Register Name: PD_CFG3 Default Description / / Default Value: 0x0000_0000 dePD27_SELECT 000: Input 010: LCD0_ VSYNC 100: Reserved 110: Reserved Reserved PD26_SELECT 000: Input 010: LCD0_ HSYNC 100: Reserved 110: Reserved / PD25_SELECT 000: Input 010: LCD0_ DE 100: Reserved 110: Reserved / PD24_SELECT 000: Input 14:12 R/W 0 nfi/ / R/W 0 / / R/W 0 / / R/W 0 11 10:8 Co7 6:4 3 2:0

ntial011: LVDS1_VPC 101: Reserved 111: Reserved 001: Output 011: SMC_SDA 101: Reserved 111: Reserved 001: Output 011: SMC_SLK 101: Reserved 111: Reserved 001: Output 011: SMC_RST 101: Reserved 111: Reserved 001: Output

Offset: 0x78 Bit Read/Write Register Name: PD_CFG3 Default Value: 0x0000_0000 Default Description 010: LCD0_CLK 100: Reserved 110: Reserved 011: SMC_VCCEN 101: Reserved 111: Reserved

1.19.4.32. PD DATA REGISTER

Offset: 0x7C Bit 31:28 Read/Write / Register Name: PD_DAT Default Description / / Default Value: 0x0000_0000 27:0 R/W 0 1.19.4.33. PD MULTI-DRIVING REGISTER 0

Offset: 0x80 Bit Co[2i+1:2i] (i=0~15) R/W 0x1 nfiRead/Write Default Description PD_DRV 00: Level 0 10: Level 2

1.19.4.34. PD MULTI-DRIVING REGISTER 1

Offset: 0x84

deRegister Name: PD_DRV0 Default Value: 0x5555_5555 Register Name: PD_DRV1 Default Value: 0x0055_5555 PD_DAT If the port is configured as input, the corresponding bit is the pin state. If the port is configured as output, the pin state is the same as the corresponding bit. The read bit value is the value setup by software. If the port is configured as functional pin, the undefined value will be read. PD[n] Multi-Driving Select (n = 0~15) 01: Level 1 11: Level 3 ntial

Bit 31:24 [2i+1:2i] (i=0~11) Read/Write / Default Description / / PD_DRV PD[n] Multi-Driving Select (n = 16~27) 10: Level 2 R/W 0x1

1.19.4.35. PD PULL REGISTER 0

Offset: 0x88 Bit [2i+1:2i] (i=0~15) Read/Write Register Name: PD_PULL0 Default Description PD_PULL Default Value: 0x0000_0000 R/W

Offset: 0x8C Bit 31:24 Co[2i+1:2i] (i=0~11) R/W 0x0 nfiRead/Write / Default Description / / PD_PULL 1.19.4.36. PD PULL REGISTER 1

1.19.4.37. PE CONFIGURE REGISTER 0

Offset: 0x90 Register Name: PE_CFG0 Default Value: 0x0000_0000

de0x0 00: Pull-up/down disable 10: Pull-down Register Name: PD_PULL1 Default Value: 0x0000_0000 10: Pull-down PD[n] Pull-up/down Select (n = 0~15) PD[n] Pull-up/down Select (n = 16~27) 00: Pull-up/down disable 01: Pull-up enable 11: Reserved ntial 11: Level 3 01: Pull-up 11: Reserved 00: Level 0 01: Level 1

Bit 31 Read/Write / Default Description / / PE7_SELECT 000: Input 001: Output 011: CSI0_D3 101: Reserved 111: Reserved 100: Reserved 110: Reserved 27 / / / PE6_SELECT 000: Input 26:24 R/W 0 010: TS0_D2 100: Reserved 110: Reserved 23 / / / de000: Input 010: TS0_D1 100: SMC_VPPEN 110: Reserved / PE4_SELECT 000: Input 010: TS0_D0 100: Reserved 110: Reserved / PE3_SELECT 000: Input 010: TS0_DVLD 100: Reserved 110: Reserved / PE2_SELECT 000: Input 010: TS0_SYNC 100: Reserved PE5_SELECT 22:20 R/W 0 19 / / nfiR/W 0 / / R/W 0 / / R/W 0 18:16 15 Co14:12 11 10:8

ntial 001: Output 011: CSI0_D2 101: Reserved 111: Reserved 001: Output 011: CSI0_D1 101: Reserved 111: Reserved 001: Output 011: CSI0_D0 111: Reserved 101: Reserved 001: Output 101: Reserved 111: Reserved 011: CSI0_VSYNC 001: Output 101: Reserved 011: CSI0_HSYNC 30:28 R/W 0 010: TS0_D3

Offset: 0x90 Bit 7 Read/Write / Register Name: PE_CFG0 Default Value: 0x0000_0000 Default Description 110: Reserved / / 111: Reserved PE1_SELECT 000: Input 6:4 R/W 0 010: TS0_ERR 100: Reserved 110: Reserved 3 / / / PE0_SELECT 000: Input 2:0 R/W 0 010: TS0_CLK 100: Reserved 110: Reserved de Register Name: PE_CFG1 Default Value: 0x0000_0000 / PE11_SELECT 000: Input 010: TS0_D7 100: Reserved 110: Reserved / PE10_SELECT 000: Input 010: TS0_D6 100: Reserved 110: Reserved /

1.19.4.38. PE CONFIGURE REGISTER 1

Offset: 0x94 Bit 31:15 nfiRead/Write / Default Description / R/W 0 / / R/W 0 / / Co11 10:8 7

ntial 001: Output 011: CSI0_CK 101: Reserved 111: Reserved 001: Output 011: CSI0_PCK 111: Reserved 101: Reserved 001: Output 011: CSI0_D7 111: Reserved 101: Reserved 001: Output 011: CSI0_D6 111: Reserved 101: Reserved

Offset: 0x94 Bit Read/Write Register Name: PE_CFG1 Default Value: 0x0000_0000 Default Description PE9_SELECT 000: Input 001: Output 6:4 R/W 0 010: TS0_D5 100: Reserved 110: Reserved 3 / / / PE8_SELECT 000: Input 2:0 R/W 0 010: TS0_D4 100: Reserved 110: Reserved 1.19.4.39. PE CONFIGURE REGISTER 2

Offset: 0x98 Bit 31:0 Read/Write /

1.19.4.40. PE CONFIGURE REGISTER 3

CoOffset: 0x98 Bit Read/Write / 31:0 / 1.19.4.41. PE DATA REGISTER

Offset: 0xA0

nfiDefault Description / / Register Name: PE_CFG2 Default Value: 0x0000_0000 Default Description / Register Name: PE_DAT Default Value: 0x0000_0000 deRegister Name: PE_CFG2 Default Value: 0x0000_0000

ntial011: CSI0_D5 101: Reserved 111: Reserved 001: Output 011: CSI0_D4 101: Reserved 111: Reserved

Bit 31:12 Read/Write / Default Description / / PE_DAT If the port is configured as input, the corresponding bit is the pin state. If the port is configured as output, the pin state is the same as the corresponding bit. The read bit value is the value setup by software. If the port is configured as functional pin, the undefined value will be read.

1.19.4.42. PE MULTI-DRIVING REGISTER 0

Offset: 0xA4 Bit 31:24 [2i+1:2i] (i=0~11) Read/Write / Register Name: PE_DRV0 Default Description / / Default Value: 0x0055_5555 R/W 1.19.4.43. PE MULTI-DRIVING REGISTER 1

Offset: 0xA8 Bit 31:0 Co/ /

1.19.4.44. PE PULL REGISTER 0

Offset: 0xAC Bit 31:24

nfiRead/Write Default Description / Read/Write / Default Description / /

dePE_DRV 0x1 00: Level 0 10: Level 2 Register Name: PE_DRV1 Default Value: 0x0000_0000 Register Name: PE_PULL0 Default Value: 0x0000_0000 PE[n] Multi-Driving Select (n = 0~15) 01: Level 1 11: Level 3 ntial11:0 R/W 0

Offset: 0xAC Bit [2i+1:2i] (i=0~11) Read/Write Register Name: PE_PULL0 Default Value: 0x0000_0000 Default Description PE_PULL 00: Pull-up/down disable 01: Pull-up 10: Pull-down PE[n] Pull-up/down Select (n = 0~11) 1.19.4.45. PE PULL REGISTER 1

Offset: 0xB0 Bit 31:0 Read/Write / Register Name: PE_PULL1 Default Description / / Default Value: 0x0000_0000 1.19.4.46. PF CONFIGURE REGISTER 0

Offset: 0xB4 Bit 31:23 Read/Write / nfiDefault Description / / PF5_SELECT 000: Input R/W 0x4 010: SDC0_D2 100: JTAG_CK1 110: Reserved / PF4_SELECT 000: Input / / R/W 0 010: SDC0_D3 100: UART0_RX 110: Reserved / PF3_SELECT / R/W / 0x4 22:20 Co19 18:16 15 14:12

deRegister Name: PF_CFG0 Default Value: 0x0040_4044 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved

ntial11: Reserved R/W 0x0

Offset: 0xB4 Bit Read/Write Register Name: PF_CFG0 Default Value: 0x0040_4044 Default Description 000: Input 001: Output 011: Reserved 111: Reserved 101: Reserved 010: SDC0_CMD 100: JTAG_DO1 110: Reserved 11 / / / PF2_SELECT 000: Input 10:8 R/W 0 010: SDC0_CLK 100: UART0_TX 110: Reserved 7 / / / PF1_SELECT 000: Input 6:4 R/W 0x4 de 010: SDC0_D0 100: JTAG_DI1 110: Reserved / PF0_SELECT 000: Input 010: SDC0_D1 100: JTAG_MS1 110: Reserved Register Name: PF_CFG1 Default Value: 0x0000_0000 / 3 / / nfiR/W 0x4 Read/Write / Default Description / 2:0

CoOffset: 0xB8 Bit 31:0 1.19.4.47. PF CONFIGURE REGISTER 1

ntial 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved

1.19.4.48. PF CONFIGURE REGISTER 2

Offset: 0xBC Bit 31:0 Read/Write / Register Name: PF_CFG2 Default Value: 0x0000_0000 Default Description / /

1.19.4.49. PF CONFIGURE REGISTER 3

Offset: 0xC0 Bit 31:0 Read/Write / Register Name: PF_CFG3 Default Description / / Default Value: 0x0000_0000 1.19.4.50. PF DATA REGISTER

Offset: 0xC4 Bit 31:6 Read/Write / 5:0 Co

Offset: 0xC8 Bit 31:12

1.19.4.51. PF MULTI-DRIVING REGISTER 0

nfiDefault Description / / PF_DAT R/W 0 Read/Write / Default Description / / deRegister Name: PF_DAT Default Value: 0x0000_0000 If the port is configured as input, the corresponding bit is the pin state. If the port is configured as output, the pin state is the same as the corresponding bit. The read bit value is the value setup by software. If the port is configured as functional pin, the undefined value will be read.

ntial

Offset: 0xC8 Bit [2i+1:2i] (i=0~5) Read/Write Register Name: PF_DRV0 Default Value: 0x0000_0555 Default Description PF_DRV 00: Level 0 10: Level 2 PF[n] Multi-Driving Select (n = 0~5)

1.19.4.52. PF MULTI-DRIVING REGISTER 1

Offset: 0xCC Bit 31:24 Read/Write / Register Name: PF_DRV1 Default Description / / Default Value: 0x0000_0000

1.19.4.53. PF PULL REGISTER 0

Offset: 0xD0 Bit 31:12 [2i+1:2i] (i=0~5) Co

Offset: 0xD4 Bit 31:0

nfiRead/Write / Default Description / / PF_PULL R/W 0x0 10: Pull-down Read/Write / Default Description / / 1.19.4.54. PF PULL REGISTER 1

deRegister Name: PF_PULL0 Default Value: 0x0000_0000 PF[n] Pull-up/down Select (n = 0~5) 00: Pull-up/down disable 01: Pull-up 11: Reserved ntial01: Level 1 11: Level 3 R/W 0x1

1.19.4.55. PG CONFIGURE REGISTER 0

Offset: 0xD8 Bit 31 Read/Write / Default Value: 0x0000_0000 Default Description / / PG7_SELECT 000: Input 30:28 R/W 0 010: TS1_D3 100: UART3_RX 110: Reserved 27 / / / 26:24 R/W 0 de000: Input 010: TS1_D2 100: UART3_TX 110: Reserved / PG5_SELECT 000: Input 010: TS1_D1 100: SDC1_D3 110: Reserved / PG4_SELECT 000: Input 010:TS1_D0 100: SDC1_D2 110: Reserved / PG3_SELECT 000: Input 010: TS1_DVLD 100: SDC1_D1 PG6_SELECT 23 / / nfiR/W 0 / / R/W 0 / / R/W 0 22:20 19 Co18:16 15 14:12

ntial 001: Output 011: CSI1_D3 101: CSI0_D11 111: Reserved 001: Output 011: CSI1_D2 101: CSI0_D10 111: Reserved 001: Output 011: CSI1_D1 111: Reserved 101: CSI0_D9 001: Output 011: CSI1_D0 101: CSI0_D8 111: Reserved 001: Output 011: CSI1_VSYNC 101: Reserved Register Name: PG_CFG0

Offset: 0xD8 Bit 11 Read/Write / Register Name: PG_CFG0 Default Value: 0x0000_0000 Default Description 110: Reserved / / 111: Reserved PG2_SELECT 000: Input 10:8 R/W 0 010: TS1_SYNC 100: SDC1_D0 110: Reserved 7 / / / PG1_SELECT 000: Input 6:4 R/W 0 010: TS1_ERR 100: SDC1_CLK 110: Reserved / 3 / / 2:0 R/W 0 nfi110: Reserved Read/Write / Default Description / / PG11_SELECT 000: Input 010: TS1_D7 R/W 0 100: UART4_RX 110: Reserved / / /

1.19.4.56. PG CONFIGURE REGISTER 1

CoOffset: 0xDC Bit 31:15 14:12 11

de PG0_SELECT 000: Input 010: TS1_CLK 100: SDC1_CMD Register Name: PG_CFG1 Default Value: 0x0000_0000 A20 User Manual (Revision 1.0) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 285 / 835

ntial 001: Output 011: CSI1_HSYNC 101: Reserved 111: Reserved 001: Output 011: CSI1_CK 101: Reserved 111: Reserved 001: Output 011: CSI1_PCK 101: Reserved 111: Reserved 001: Output 011: CSI1_D7 111: Reserved 101: CSI0_D15

Offset: 0xDC Bit Read/Write Register Name: PG_CFG1 Default Value: 0x0000_0000 Default Description PG10_SELECT 000: Input 001: Output 10:8 R/W 0 010: TS1_D6 100: UART4_TX 110: Reserved 7 / / / PG9_SELECT 000: Input 6:4 R/W 0 010:TS1_D5 100: UART3_CTS 110: Reserved 3 / / / 2:0 R/W 0 dePG8_SELECT 000: Input 010: TS1_D4 100: UART3_RTS 110: Reserved Register Name: PG_CFG2 Default Value: 0x0000_0000 / Register Name: PG_CFG3 Default Value: 0x0000_0000 1.19.4.57. PG CONFIGURE REGISTER 2

Offset: 0xE0 Bit Co31:0 / /

1.19.4.58. PG CONFIGURE REGISTER 3

Offset: 0xE4 Bit

nfiRead/Write Default Description Read/Write Default Description

ntial011: CSI1_D6 101: CSI0_D14 111: Reserved 001: Output 011: CSI1_D5 101: CSI0_D13 111: Reserved 001: Output 011: CSI1_D4 101: CSI0_D12 111: Reserved

Offset: 0xE4 Bit 31:0 Read/Write / Register Name: PG_CFG3 Default Value: 0x0000_0000 Default Description / / 1.19.4.59. PG DATA REGISTER

Offset: 0xE8 Bit 31:12 Read/Write / Register Name: PG_DAT Default Description / / Default Value: 0x0000_0000 PG_DAT 11:0 R/W 0

Offset: 0xEC Bit 31:20 Co[2i+1:2i] (i=0~11) R/W 0x1 nfiRead/Write / Default Description / / PG_DRV 00: Level 0 10: Level 2 1.19.4.60. PG MULTI-DRIVING REGISTER 0

1.19.4.61. PG MULTI-DRIVING REGISTER 1

Offset: 0xF0

deRegister Name: PG_DRV0 Default Value: 0x0555_5555 Register Name: PG_DRV1 Default Value: 0x0000_0000 If the port is configured as input, the corresponding bit is the pin state. If the port is configured as output, the pin state is the same as the corresponding bit. The read bit value is the value setup by software. If the port is configured as functional pin, the undefined value will be read. PG[n] Multi-Driving Select (n = 0~11) 01: Level 1 11: Level 3 ntial

Bit 31:24 Read/Write / Default Description / /

1.19.4.62. PG PULL REGISTER 0

Offset: 0xF4 Bit 31:24 [2i+1:2i] (i=0~11) Read/Write / Register Name: PG_PULL0 Default Description / / Default Value: 0x0000_0000 PG_PULL R/W 0x0 PG[n] Pull-up/down Select (n = 0~11) 00: Pull-up/down disable 01: Pull-up 10: Pull-down 1.19.4.63. PG PULL REGISTER 1

Offset: 0xF8 Bit 31:0

CoOffset: 0xFC Bit 31 Read/Write / / 30:28 R/W 0

1.19.4.. PH CONFIGURE REGISTER 0

nfiRead/Write / Default Description / / Default Description / PH7_SELECT 000: Input 010: LCD1_D7 100: UART5_RX deRegister Name: PG_PULL1 Default Value: 0x0000_0000 Register Name: PH_CFG0 Default Value: 0x0000_0000 001: Output 011: Reserved 101: MS_CLK

ntial11: Reserved

Offset: 0xFC Bit 27 Read/Write / Register Name: PH_CFG0 Default Value: 0x0000_0000 Default Description 110: EINT7 / / 111: CSI1_D7 PH6_SELECT 000: Input 26:24 R/W 0 010: LCD1_D6 100: UART5_TX 110: EINT6 23 / / / PH5_SELECT 000: Input 22:20 R/W 0 010: LCD1_D5 100: UART4_RX 110: EINT5 / 19 / / 18:16 R/W 0 de PH4_SELECT 000: Input 010: LCD1_D4 100: UART4_TX 110: EINT4 / PH3_SELECT 000: Input 010: LCD1_D3 110: EINT3 / PH2_SELECT 000: Input 100: UART3_CTS 010: LCD1_D2 100: UART3_RTS 110: EINT2 / PH1_SELECT nfi/ / R/W 0 / / R/W 0 / R/W / 0 15 14:12 Co11 10:8 7 6:4

ntial 001: Output 011: Reserved 101: MS_BS 111: CSI1_D6 001: Output 011: Reserved 101: Reserved 111: CSI1_D5 001: Output 011: Reserved 101: Reserved 111: CSI1_D4 001: Output 011: Reserved 101: Reserved 111: CSI1_D3 001: Output 011: Reserved 101: Reserved 111: CSI1_D2

Offset: 0xFC Bit Read/Write Register Name: PH_CFG0 Default Value: 0x0000_0000 Default Description 000: Input 001: Output 011: Reserved 101: Reserved 111: CSI1_D1 010: LCD1_D1 100: UART3_RX 110: EINT1 3 / / / PH0_SELECT 000: Input 2:0 R/W 0 010: LCD1_D0 100: UART3_TX 110: EINT0

1.19.4.65. PH CONFIGURE REGISTER 1

Offset: 0x100 Bit 31 Read/Write / Default Description / / nfiPH15_SELECT 000: Input R/W 0 010: LCD1_D15 100: KP_IN5 110: EINT15 / / / PH14_SELECT 000: Input 100: KP_IN4 110: EINT14 / PH13_SELECT 000: Input R/W 0 010: LCD1_D14 / / R/W 0 010: LCD1_D13 30:28 Co26:24 23 22:20

deRegister Name: PH_CFG1 Default Value: 0x0000_0000 001: Output 011: ETXD2 101: SMC_VPPPP 111: CSI1_D15 001: Output 011: ETXD3 101: SMC_VPPEN 111: CSI1_D14 001: Output 011: Reserved ntial 001: Output 011: Reserved 101: Reserved 111: CSI1_D0

Offset: 0x100 Bit Read/Write Register Name: PH_CFG1 Default Value: 0x0000_0000 Default Description 100: PS2_SDA1 110: EINT13 101: SMC_RST 111: CSI1_D13 19 / / / PH12_SELECT 000: Input 18:16 R/W 0 010: LCD1_D12 110: EINT12 100: PS2_SCK1 15 / / / PH11_SELECT 000: Input 14:12 R/W 0 100: KP_IN3 110: EINT11 / 010: LCD1_D11 11 / / nfi100: KP_IN2 110: EINT10 / / / PH9_SELECT 000: Input 100: KP_IN1 110: EINT9 / PH8_SELECT 000: Input 100: KP_IN0 110: EINT8 R/W 0 010: LCD1_D9 / / R/W 0 010: LCD1_D8 10:8 R/W 0 7 Co3 2:0 6:4 de PH10_SELECT 000: Input 010: LCD1_D10

ntial 001: Output 011: Reserved 101: Reserved 111: CSI1_D12 001: Output 011: ERXD0 101: MS_D3 111: CSI1_D11 001: Output 011: ERXD1 101: MS_D2 111: CSI1_D10 001: Output 011: ERXD2 101: MS_D1 111: CSI1_D9 001: Output 011: ERXD3 101: MS_D0 111: CSI1_D8

1.19.4.66. PH CONFIGURE REGISTER 2

Offset: 0x104 Bit 31 Read/Write / Register Name: PH_CFG2 Default Value: 0x0000_0000 Default Description / / PH23_SELECT 000: Input 30:28 R/W 0 010: LCD1_D23 100: KP_OUT3 110: Reserved 27 / / / PH22_SELECT 000: Input 26:24 R/W 0 010: LCD1_D22 100: KP_OUT2 110: Reserved / de PH21_SELECT 000: Input 010: LCD1_D21 100: CAN_RX 110: EINT21 / PH20_SELECT 000: Input 010: LCD1_D20 100: CAN_TX 110: EINT20 / PH19_SELECT 000: Input 010: LCD1_D19 100: KP_OUT1 110: EINT19 / PH18_SELECT 23 / / nfi/ / R/W 0 / / R/W 0 / R/W / 0 22:20 R/W 0 19 18:16 Co15 14:12 11 10:8

ntial 001: Output 011: ETXEN 101: SDC1_CLK 111: CSI1_D23 001: Output 011: EMDIO 101: SDC1_CMD 111: CSI1_D22 001: Output 011: EMDC 101: Reserved 111: CSI1_D21 001: Output 011: ERXDV 101: Reserved 111: CSI1_D20 001: Output 011: ERXERR 101: SMC_SDA 111: CSI1_D19

Offset: 0x104 Bit Read/Write Register Name: PH_CFG2 Default Value: 0x0000_0000 Default Description 000: Input 001: Output 011: ERXCK 101: SMC_SCK 111: CSI1_D18 010: LCD1_D18 100: KP_OUT0 110: EINT18 7 / / / PH17_SELECT 000: Input 6:4 R/W 0 100: KP_IN7 110: EINT17 3 / / / 010: LCD1_D17 PH16_SELECT 000: Input 100: KP_IN6 110: EINT16 2:0 R/W 0 1.19.4.67. PH CONFIGURE REGISTER 3

Offset: 0x108 Bit 31:15 Co14:12 R/W 0 11 / / 10:8 R/W 0

nfiRead/Write / Default Description / / PH27_SELECT 000: Input 100: KP_OUT7 110: Reserved Reserved PH26Select 000: Input

de 010: LCD1_D16 Register Name: PH_CFG3 Default Value: 0x0000_0000 010: LCD1_ VSYNC 010: LCD1_HSYNC A20 User Manual (Revision 1.0) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 293 / 835

ntial 001: Output 011: ETXD0 101: SMC_VCCEN 111: CSI1_D17 001: Output 011: ETXD1 101: Reserved 111: CSI1_D16 001: Output 011: ETXERR 101: SDC1_D3 111: CSI1_VSYNC 001: Output 011: ECOL

Offset: 0x108 Bit Read/Write Register Name: PH_CFG3 Default Value: 0x0000_0000 Default Description 100: KP_OUT6 110: Reserved 101: SDC1_D2 111: CSI1_HSYNC 7 / / / PH25_SELECT 000: Input 6:4 R/W 0 010: LCD1_DE 100: KP_OUT5 110: Reserved 3 / / / PH24_SELECT 000: Input 2:0 R/W 0 010: LCD1_CLK 100: KP_OUT4 110: Reserved de Register Name: PH_DAT Default Value: 0x0000_0000 / PH_DAT Register Name: PH_DRV0 Default Value: 0x5555_5555

1.19.4.68. PH DATA REGISTER

Offset: 0x10C Bit 31:28 Co27:0 R/W 0

1.19.4.69. PH MULTI-DRIVING REGISTER 0

Offset: 0x110

Bit [2i+1:2i] (i=0~15) Read/Write Default Description PH_DRV PH[n] Multi-Driving Select (n = 0~15) 00: Level 0 10: Level 2 01: Level 1 11: Level 3 R/W 0x1

PH MULTI-DRIVING REGISTER 1

Offset: 0x114 Bit 31:24 [2i+1:2i] (i=0~11) Read/Write / Register Name: PH_DRV1 Default Description / / Default Value: 0x0055_5555 PH_DRV R/W 0x1 PH[n] Multi-Driving Select (n = 16~27) 00: Level 0 10: Level 2 01: Level 1 11: Level 3

1.19.4.70. PH PULL REGISTER 0

Offset: 0x118 Bit [2i+1:2i] (i=0~15) nfiRead/Write Default Description PH_PULL R/W 0x0 10: Pull-down Read/Write / Default Description / / Co

Offset: 0x11C Bit 31:24

1.19.4.71. PH PULL REGISTER 1

deRegister Name: PH_PULL0 Default Value: 0x0000_0000 PH[n] Pull-up/down Select (n = 0~15) 00: Pull-up/down disable 01: Pull-up 11: Reserved ntial

Offset: 0x11C Bit [2i+1:2i] (i=0~11) Read/Write Register Name: PH_PULL1 Default Value: 0x0000_0000 Default Description PH_PULL 00: Pull-up/down disable 01: Pull-up enable 10: Pull-down 11: Reserved PH[n] Pull-up/down Select (n = 16~27)

1.19.4.72. PI CONFIGURE REGISTER 0

Offset: 0x120 Bit 31 Read/Write / Register Name: PI_CFG0 Default Description / / Default Value: 0x0000_0000 30:28 R/W 0 dePI7_SELECT 000: Input 010: SDC3_D1 100: Reserved 110: Reserved / PI6_SELECT 000: Input 010: SDC3_D0 100: Reserved 110: Reserved / PI5_SELECT 000: Input 010: SDC3_CLK 100: Reserved 110: Reserved / PI4_SELECT 000: Input 010: SDC3_CMD 27 nfi/ / R/W 0 / / R/W 0 / / R/W 0 26:24 Co22:20 19 18:16

ntial001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved R/W 0x0

Offset: 0x120 Bit Read/Write Register Name: PI_CFG0 Default Value: 0x0000_0000 Default Description 100: Reserved 110: Reserved 101: Reserved 111: Reserved 15 / / / PI3_SELECT 000: Input 14:12 R/W 0 010: PWM1 100: Reserved 110: Reserved 11 / / / PI2_SELECT 000: Input 10:8 R/W 0 010: Reserved 100: Reserved 110: Reserved / de PI1_SELECT 000: Input 010: Reserved 100: Reserved 110: Reserved / PI0_SELECT 000: Input 010: Reserved 100: Reserved 110: Reserved Register Name: PI_CFG1 Default Value: 0x0000_0000 7 / / nfi/ / R/W 0 Read/Write Default Description 6:4 R/W 0 3 Co

Offset: 0x124 Bit

2:0 1.19.4.73. PI CONFIGURE REGISTER 1

ntial 001: Output 011: TWI4_SDA 101: Reserved 111: Reserved 001: Output 011: TWI4_SCK 111: Reserved 101: Reserved 001: Output 011: TWI3_SDA 101: Reserved 111: Reserved 001: Output 011: TWI3_SCK 111: Reserved 101: Reserved

Offset: 0x124 Bit 31 Read/Write / Register Name: PI_CFG1 Default Value: 0x0000_0000 Default Description / / 000: Input 30:28 R/W 0 010: SPI1_CS1 100: TCLKIN1 110: EINT27 27 / / / PI14_SELECT 000: Input 26:24 R/W 0 010: SPI0_CS1 100: TCLKIN0 110: EINT26 23 / / 22:20 R/W 0 de/ PI13_SELECT 000: Input 010: SPI0_MISO 110: EINT25 / 100: CLK_OUT_B PI12_SELECT 000: Input 010: SPI0_MOSI 110: EINT24 / PI11_SELECT 000: Input 100: CLK_OUT_A 010: SPI0_CLK 100: Reserved 110: EINT23 / PI10_SELECT 000: Input 19 nfi/ / R/W 0 / / R/W 0 / / R/W 0 18:16 Co15 14:12 11 10:8

ntial 001: Output 011: PS2_SDA1 111: Reserved 101: Reserved 001: Output 011: PS2_SCK1 101: Reserved 111: Reserved 001: Output 011: UART6_RX 101: Reserved 111: Reserved 001: Output 011: UART6_TX 101: Reserved 111: Reserved 001: Output 011: UART5_RX 101: Reserved 111: Reserved 001: Output PI15_SELECT

Offset: 0x124 Bit Read/Write Register Name: PI_CFG1 Default Value: 0x0000_0000 Default Description 010: SPI0_CS0 100: Reserved 110: EINT22 011: UART5_TX 101: Reserved 111: Reserved 7 / / / PI9_SELECT 000: Input 6:4 R/W 0 010: SDC3_D3 100: Reserved 110: Reserved 3 / / / PI8_SELECT 000: Input 2:0 R/W 0 de010: SDC3_D2 100: Reserved 110: Reserved Register Name: PI_CFG2 Default Value: 0x0000_0000 / PI21_SELECT 000: Input 100: HSDA / PI20_SELECT 000: Input 100: HSCL 010: PS2_SDA0 110: Reserved 010: PS2_SCK0

1.19.4.74. PI CONFIGURE REGISTER 2

Offset: 0x128 Bit 31:23 Co22:20 R/W 0 19 / / 18:16 R/W 0

ntial 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: Reserved 101: Reserved 111: Reserved 001: Output 011: UART7_RX 101: Reserved 111: Reserved 001: Output 011: UART7_TX 101: Reserved

Offset: 0x128 Bit 15 Read/Write / Register Name: PI_CFG2 Default Value: 0x0000_0000 Default Description 110: Reserved / / 111: Reserved PI19_SELECT 000: Input 14:12 R/W 0 010: SPI1_MISO 100: Reserved 110: EINT31 11 / / / PI18_SELECT 000: Input 10:8 R/W 0 010: SPI1_MOSI 100: Reserved 110: EINT30 / 7 / / 6:4 R/W 0 nfi110: EINT29 / / / PI16_SELECT 000: Input R/W 0 010: SPI1_CS0 100: Reserved 110: EINT28 Read/Write / Default Description / / 3 2:0 Co

Offset: 0x12C Bit 31:0

1.19.4.75. PI CONFIGURE REGISTER 3

de PI17_SELECT 000: Input 010: SPI1_CLK 100: Reserved ntial 001: Output 011: UART2_RX 101: Reserved 111: Reserved 001: Output 011: UART2_TX 101: Reserved 111: Reserved 001: Output 011: UART2_CTS 101: Reserved 111: Reserved 001: Output 011: UART2_RTS 101: Reserved 111: Reserved

1.19.4.76. PI DATA REGISTER

Offset: 0x130 Bit 31:22 Read/Write / Default Value: 0x0000_0000 Default Description / / PI_DAT 21:0 R/W 0 If the port is configured as input, the corresponding bit is the pin state. If the port is configured as output, the pin state is the same as the corresponding bit. The read bit value is the value setup by software. If the port is configured as functional pin, the undefined value will be read.

1.19.4.77. PI MULTI-DRIVING REGISTER 0

Offset: 0x134 Bit [2i+1:2i] Read/Write (i=0~15) nfiPI_DRV R/W 0x1 00: Level 0 10: Level 2 Read/Write / Default Description / Reserved PI_DRV R/W 0x1 00: Level 0

CoOffset: 0x138 Bit 31:12 [2i+1:2i] (i=0~5)

1.19.4.78. PI MULTI-DRIVING REGISTER 1

deRegister Name: PI_DRV0 Default Description Default Value: 0x5555_5555 PI[n] Multi-Driving Select (n = 0~15) 01: Level 1 11: Level 3 PI[n] Multi-Driving Select (n = 16~21) 01: Level 1 ntialRegister Name: PI_DAT

Offset: 0x138 Bit Read/Write Register Name: PI_DRV1 Default Value: 0x0000_0000 Default Description 10: Level 2 11: Level 3 1.19.4.79. PI PULL REGISTER 0

Offset: 0x13C Bit 31:26 [2i+1:2i] (i=0~12) Read/Write / Register Name: PI_PULL0 Default Description / / Default Value: 0x0000_0000 PI_PULL R/W 0x0 PI[n] Pull-up/down Select (n = 0~12) 10: Pull-down

1.19.4.80. PI PULL REGISTER 1

Offset: 0x140 Bit 31:0

CoOffset: 0x200 Bit Read/Write [4i+3:4i] (i=0~7) R/W 0

1.19.4.81. PIO INTERRUPT CONFIGURE REGISTER 0

nfiRead/Write / Default Description / / Default Description PIO_INT_CFG deRegister Name: PI_PULL1 Default Value: 0x0000_0000 External INTn Mode (n = 0~7) 0x0: Positive Edge 0x1: Negative Edge 00: Pull-up/down disable 01: Pull-up ntial11: Reserved

Offset: 0x200 Bit Read/Write Register Name: PIO_INT_CFG0 Default Value: 0x0000_0000 Default Description 0x2: High Level 0x3: Low Level 0x4: Double Edge (Positive/ Negative) Others: Reserved

1.19.4.82. PIO INTERRUPT CONFIGURE REGISTER 1

Offset: 0x204 Bit Read/Write Register Name: PIO_INT_CFG1 Default Value: 0x0000_0000 Default Description [4i+3:4i] (i=0~7) R/W

1.19.4.83. PIO INTERRUPT CONFIGURE REGISTER 2

CoOffset: 0x208 Bit Read/Write [4i+3:4i] (i=0~7) R/W 0

nfiOthers: Reserved Default Description PIO_INT_CFG 0x2: High Level 0x3: Low Level de0x0: Positive Edge 0x2: High Level 0x3: Low Level 0 0x1: Negative Edge Default Value: 0x0000_0000 0x0: Positive Edge 0x1: Negative Edge PIO_INT_CFG External INTn Mode (n = 8~15) 0x4: Double Edge (Positive/ Negative) Register Name: PIO_INT_CFG2 External INTn Mode (n = 16~23) 0x4: Double Edge (Positive/ Negative) ntial

Offset: 0x208 Bit Read/Write Register Name: PIO_INT_CFG2 Default Value: 0x0000_0000 Default Description Others: Reserved 1.19.4.84. PIO INTERRUPT CONFIGURE REGISTER 3

Offset: 0x20C Bit Read/Write Register Name: PIO_INT_CFG3 Default Value: 0x0000_0000 Default Description PIO_INT_CFG External INTn Mode (n = 24~31) 0x0: Positive Edge [4i+3:4i] (i=0~7) R/W 0 0x2: High Level 0x3: Low Level 0x1: Negative Edge 1.19.4.85. PIO INTERRUPT CONTROL REGISTER

Offset: 0x210 Bit Register Name: PIO_INT_CTL Default Value: 0x0000_0000 Co[n] (n=0~31) R/W 0

nfiRead/Write Default Description PIO_INT_CTL 0: Disable 1: Enable

deOthers: Reserved 0x4: Double Edge (Positive/ Negative) External INTn Enable (n = 0~31) ntial

1.19.4.86. PIO INTERRUPT STATUS REGISTER

Offset: 0x214 Bit Read/Write Register Name: PIO_INT_STATUS Default Value: 0x0000_0000 PIO_INT_STATUS [n] (n=0~31) R/W 0 0: No IRQ pending 1: IRQ pending Write ‘1’ to clear External INTn Pending Bit (n = 0~31)

1.19.4.87. PIO INTERRUPT DEBOUNCE REGISTER

Offset: 0x218 Bit 31:7 6:4 3:1 Read/Write / R/W / 0 Co

nfi/ / R/W 0 0: LOSC 32Khz 1: HOSC 24Mhz deDefault Value: 0x0000_0000 Default Description / / DEB_CLK_PRE_SCALE 0 Debounce Clock Pre-scale n PIO_INT_CLK_SELECT PIO Interrupt Clock Select Register Name: PIO_INT_DEB The selected clock source is prescaled by 2^n. ntialDefault Description

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