Digital repetition rate check circuit

专利名称：Digital repetition rate check circuit发明人：Edward M. Horiuchi,Jose V. Souto Martins申请号：US05/539481申请日：19750108公开号：US03942125A公开日：19760302

摘要：A pulse repetition rate check circuit of the type which detects when the secondof two consecutive pulses from a pulse generator is early or late with respect to apredetermined repetition time period includes an early pulse detector, first and secondearly pulse detector enabling means and first and second clocks. Each early pulsedetector enabling means enables the early pulse detector responsive to its associatedclock for a predetermined time so that a second pulse occurring within the

predetermined time is detected as an early second pulse. The early pulse detectorenabling means includes an inhibit means for preventing the enabling of the early pulsedetector after it has been once enabled. A steering circuit alternately directs the clockingsignals from an oscillator to the clocks responsive to alternate pulses and a clock resetmeans associated with each clock causes each clock to be reset responsive to the otherclock to assure that one clock is always conditioned to act upon the receipt of the nextpulse. The pulse repetition rate check circuit also includes first and second late pulsedetectors which are coupled to the first and second clocks respectively for providing anerror signal indicating that the second pulse is late should the second pulse fail to occurwithin the predetermined repetition time period.

申请人：GTE AUTOMATIC ELECTRIC LABORATORIES INCORPORATED

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