PCM3060资料

BurrĆBrown Productsfrom Texas Instruments

PCM3060

SLAS533–MARCH2007

24-BIT,96/192-kHzASYNCHRONOUSSTEREOAUDIOCODEC

FEATURES

•••

24-BitDelta-SigmaADCandDACADC,DACAsynchronousOperationStereoADC:

–HighPerformance:(Typical,48kHz)–THD+N:–93dB–SNR:99dB

–DynamicRange:99dB–SamplingRate:16–96kHz

–SystemClock:256,384,512,768fS–FullScaleInput:3Vp-p–AntialiasingFilterIncluded–1/DecimationFilter:

–Pass-BandRipple:±0.05dB–Stop-BandAttenuation:–65dB–On-ChipHigh-PassFilter:0.91HzatfS=48kHzStereoDAC:

–HighPerformance:(Typical,Differential,48kHz)

–THD+N:–94dB–SNR:105dB

–DynamicRange:104dB–SamplingRate:16–192kHz

–SystemClock:128,192,256,384,512,768fS

–DifferentialVoltageOutput:8Vp-p–Single-EndedVoltageOutput:4Vp-p–AnalogLow-PassFilterIncluded–4×/8×OversamplingDigitalFilter:–Pass-BandRipple:±0.04dB–Stop-BandAttenuation:–50dB–ZeroFlags

FlexibleModeControl

–3-WireSPI,2-WireI2CCompatibleSerialControlInterface

–HardwareControlMode

MultipleFunctionsviaSPIorI2CInterface:–DigitalAttenuationandSoftMuteforADCandDAC

–DigitalDe-Emphasis:32,44.1,48kHzfor

DAC

–PowerDown:ADC/DACIndependently–Asynchronous/SynchronousControlfor

ADC/DACOperation

ExternalResetandPower-DownPin:–ADC/DACSimultaneouslyAudioInterfaceMode:

–ADC/DACIndependentMaster/SlaveAudioDataFormat:

–ADC/DACIndependent

–I2S,Left-Justified,Right-JustifiedDualPowerSupplies:

–5-VforAnalogand3.3-VforDigitalPackage:TSSOP-28

•••

••

APPLICATIONS

••••

DVD-RWDigitalTV

DigitalSet-TopBox

Audio-VisualApplications

•

DESCRIPTION

ThePCM3060isalow-cost,high-performance,single-chip,24-bitstereoaudiocodecwithsingle-endedanaloginputsanddifferentialanalogoutputs.

Thestereo24-bitADCemploysa-timesdelta-sigmamodulator.Itsupports16–96kHzsamplingratesanda16/24-bitdigitalaudiooutputwordontheaudiointerface.

Thestereo24-bitDACemploysa-or128-timesdelta-sigmamodulator.Itsupports16–192kHzsamplingratesanda16/24-bitdigitalaudioinputwordontheaudiointerface.

ThePCM3060supportsfullyindependentoperationofthesamplingrateandaudiointerfacefortheADCandDAC.

EachaudiointerfacesupportsI2S,left-justified,andright-justifiedformatswith16/24-bitwords.

•

•

Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.

PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.

Copyright©2007,TexasInstrumentsIncorporated

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ThisintegratedcircuitcanbedamagedbyESD.TexasInstrumentsrecommendsthatallintegratedcircuitsbehandledwithappropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.

ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemoresusceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.

DESCRIPTION(CONTINUED)

ThePCM3060canbesoftware-controlledthrougha3-wireSPI-compatibleor2-wireI2C-compatibleserialinterface,whichprovidesaccesstoallfunctionsincludingdigitalattenuation,softmute,de-emphasisetc.ThePCM3060canbealsousedinhardwaremode,whichprovidesthreebasicfunctions.

ThePCM3060isfabricatedusingahighlyadvancedCMOSprocessandisavailableinasmall28-pinTSSOPpackage.

ThePCM3060issuitableforvarioussoundprocessingapplicationsforDVD-RW,digitalTV,STB,andotherAVequipment.

ABSOLUTEMAXIMUMRATINGS

overoperatingfree-airtemperaturerange(unlessotherwisenoted)

VCCVDD

AGND1,AGND2,DGND,SGNDRST,MS,MC,MD,SCKI1,SCKI2,DIN

DigitalinputvoltageAnaloginputvoltage

TATstgTJ

BCK1,BCK2,LRCK1,LRCK2,DOUTZEROL,ZEROR,MODE

VINL,VINR,VCOM,VOUTL+,VOUTL–,VOUTR+,VOUTR–

Inputcurrent(anypinsexceptsupplies)AmbienttemperatureunderbiasStoragetemperatureJunctiontemperatureLeadtemperature(soldering)

Packagetemperature(IRreflow,peak)

(1)

(1)

VALUE

Supplyvoltage

Groundvoltagedifferences

–0.3to6.5–0.3to4±0.1–0.3to6.5

–0.3to(VDD+0.3V)<4–0.3to(VDD+0.3V)<4–0.3to(VCC+0.3V)<6.5

±10–40to125–55to150

150260,5s260

UNITVVVVVVmA°C°C°C°C°C

Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratingsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.

RECOMMENDEDOPERATINGCONDITIONS

overoperatingfree-airtemperaturerange(unlessotherwisenoted)

MIN

VCCVDD

AnalogsupplyvoltageDigitalsupplyvoltageDigitalinputinterfacelevelDigitalinputclockfrequencyAnaloginputlevel

AnalogoutputloadresistanceAnalogoutputloadcapacitanceDigitaloutputloadcapacitanceOperatingfree-airtemperature

–25

25

AC-coupledDC-coupled

510

502085

Samplingfrequency,LRCK1,LRCK2Systemclockfrequency,SCKI1,SCKI2

4.52.7162.048

3NOM

53.3

MAX5.53.696/19236.8

UNITVVkHzMHzVppkΩkΩpFpF°C

TTLcompatible

2

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ELECTRICALCHARACTERISTICS

AllspecificationsatTA=25°C,VCC=5V,VDD=3.3V,fS=48kHz,SCKI1=SCKI2=512fS,24-bitdata(unlessotherwisenoted).

PARAMETER

DIGITALINPUT/OUTPUTDATAFORMAT

AudiodatainterfaceformatAudiodatawordlengthAudiodataformat

fS

Samplingfrequency,ADCSamplingfrequency,DACSystemclockfrequency

INPUTLOGICVIH

(1)

TESTCONDITIONS

PCM3060PWMIN

TYP

MAX

UNIT

I2S,LJ,RJ16,24

MSB-first,2s-complement1616

128,192,256,384,512,768fS

2.048

2

4848

9619236.8VDD0.8

2

VIN=VDD

5.50.8±10±10

65

100±10

2.8

0.5

0.5VCC

7

12.5

18±1

µA

VIN=0VVIN=VDDVIN=0VIOUT=–4mAIOUT=4mA

VDCkHzMHzBits

VIL(1)VIH(2)(3)VIL(2)(3)IIH(2)IIL(2)IIH(1)IIL(1)

(3)(3)

Inputlogiclevel

Inputlogiccurrent

OUTPUTLOGICVOH(4)VOL(4)(5)

Outputlogiclevel

VDC

REFERENCEOUTPUT

VCOMoutputvoltageVCOMoutputimpedanceAllowableVCOMoutputsource/sinkcurrent

ADCCHARACTERISTICS

Resolution

ANALOGINPUT

FullscaleinputvoltageCentervoltageInputimpedance

Antialiasingfilterresponse

DCACCURACY

Gainmismatch,channel-to-channelGainerrorBipolarzeroerror

(1)(2)(3)(4)(5)

Full-scaleinput,VINL,VINRFull-scaleinput,VINL,VINRHPFbypass,VINL,VINR

±2±2±0.5

±8±8±2

%ofFSR%ofFSR%ofFSR

–3dB

VINL,VINR=0dB

0.6VCC0.5VCC

10300

Vp-pVkΩkHz

16

24

BitsVkΩµA

BCK1,BCK2,LRCK1,LRCK2(inslavemode,Schmitt-triggerinputwith50-kΩtypicalinternalpulldownresistor)SCKI1,SCKI2,DIN,MS/ADR/IFMD,MC/SCL/FMT,MD/SDA/IFMD(Schmitt-triggerinput,5-Vtolerant).RST(Schmitt-triggerinputwith50-kΩtypicalinternalpulldownresistor,5-Vtolerant).BCK1,BCK2,LRCK1,LRCK2(inmastermode),DOUT,ZEROL,ZERORMD/SDA/IFMD(inI2Cmode,opendrainLOWoutput)

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ELECTRICALCHARACTERISTICS(continued)

AllspecificationsatTA=25°C,VCC=5V,VDD=3.3V,fS=48kHz,SCKI1=SCKI2=512fS,24-bitdata(unlessotherwisenoted).

PARAMETER

DYNAMICPERFORMANCETHD+N

(6)(7)

TESTCONDITIONS

PCM3060PWMIN

TYP–93–93

95959292

9910199101969698

0.454

fS

0.583

fS

MAX–85

UNIT

Totalharmonicdistortion+noiseDynamicrange

VIN=–1dB,fS=48kHzVIN=–1dB,fS=96kHzfS=48kHz,A-weightedfS=96kHz,A-weightedfS=48kHz,A-weightedfS=96kHz,A-weightedfS=48kHzfS=96kHz

fS1=48kHz,fS2=44.1kHzfS1=96kHz,fS2=44.1kHz

dBdBdBdBdB

SNRSignal-to-noiseratioChannelseparation

(betweenL-chandR-ch)CrosstalkfromDAC

DIGITALFILTERPERFORMANCE

PassbandStopbandPass-bandrippleStop-bandattenuationGroupdelaytimeHPFfrequencyresponse

DACCHARACTERISTICS

Resolution

ANALOGOUTPUT

OutputvoltageCentervoltageLoadimpedance

Single-endedDifferentialSingle-endedDifferentialAC-coupledDC-coupledf=20kHz

LPFfrequencyresponse

DCACCURACY

Gainmismatch,channel-to-channelGainerrorBipolarzeroerror

(6)(7)

Single-ended

Differential(VOUTX+–VOUTX–)

±1±2±1±1

±4±6±2

%ofFSR%ofFSR%ofFSR

f=44kHz–3dB

510

–0.02–0.073000.8VCC1.6VCC0.5VCC0.48VCC

Vp-pVkΩdBkHz

16

24

Bits

–3dB<0.454fS>0.583fS

–65

17.4/fS0.019fS/1000

HzHz

±0.05

dBdBsHz

fIN=1kHz,usingSystemTwoaudiomeasurementsystembyAudioPrecision,RMSmodewith20-kHzLPFand400-HzHPF.fS=96kHz:SCKI1=SCKI2=256fS,fS=192kHz:SCKI1=512fSatfS=48kHzandSCKI2=128fSatfS=192kHz.

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ELECTRICALCHARACTERISTICS(continued)

AllspecificationsatTA=25°C,VCC=5V,VDD=3.3V,fS=48kHz,SCKI1=SCKI2=512fS,24-bitdata(unlessotherwisenoted).

PARAMETER

DYNAMICPERFORMANCE(SINGLE-ENDED)THD+N

(8)(9)(10)

TESTCONDITIONS

PCM3060PWMIN

TYP–93–94–94

99

103103103

100

104104104

97

101101101

97

101101101–94–95–95104104104105105105103103103103103103

0.454

fS

0.546

fS

MAX–85

UNIT

VOUT=0dB,fS=48kHz

Totalharmonicdistortion+noiseVOUT=0dB,fS=96kHz

VOUT=0dB,fS=192kHzfS=48kHz,EIAJ,A-weighted

Dynamicrange

fS=96kHz,EIAJ,A-weightedfS=192kHz,EIAJ,A-weightedfS=48kHz,EIAJ,A-weighted

SNR

Signal-to-noiseratio

fS=96kHz,EIAJ,A-weightedfS=192kHz,EIAJ,A-weightedfS=48kHz

Channelseparation

fS=96kHzfS=192kHz

fS1=48kHz,fS2=44.1kHz

CrosstalkfromADC

DYNAMICPERFORMANCE(DIFFERENTIAL)THD+N

fS1=48kHz,fS2=88.2kHzfS1=48kHz,fS2=176.4kHz

(8)(9)(11)

dB

dB

dB

dB

dB

VOUT=0dB,fS=48kHz

Totalharmonicdistortion+noiseVOUT=0dB,fS=96kHz

VOUT=0dB,fS=192kHzfS=48kHz,EIAJ,A-weighted

Dynamicrange

fS=96kHz,EIAJ,A-weightedfS=192kHz,EIAJ,A-weightedfS=48kHz,EIAJ,A-weighted

SNR

Signal-to-noiseratio

fS=96kHz,EIAJ,A-weightedfS=192kHz,EIAJ,A-weightedfS=48kHz

Channelseparation

fS=96kHzfS=192kHz

fS1=48kHz,fS2=44.1kHz

CrosstalkfromADC

DIGITALFILTERPERFORMANCE

PassbandStopbandPass-bandrippleStop-bandattenuation

(8)(9)(10)(11)

<0.454fS>0.546fS

–50

fS1=48kHz,fS2=88.2kHzfS1=48kHz,fS2=176.4kHz

SHARPROLLOFF

dB

dB

dB

dB

dB

HzHz

±0.04dBdB

fS=96kHz:SCKI1=SCKI2=256fS,fS=192kHz:SCKI1=512fSatfS=48kHzandSCKI2=128fSatfS=192kHz.

fOUT=1kHz,usingSystemTwoaudiomeasurementsystembyAudioPrecision,RMSmodewith20-kHzLPFand400-HzHPF.Assumed5-kΩAC-coupledsecond-orderLPFand115-dBorhigher-performancebuffer.

Assumed10-kΩDC-coupledsecond-orderLPFand115-dBorhigher-performancedifferentialtosingle-endedconverter.

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ELECTRICALCHARACTERISTICS(continued)

AllspecificationsatTA=25°C,VCC=5V,VDD=3.3V,fS=48kHz,SCKI1=SCKI2=512fS,24-bitdata(unlessotherwisenoted).

PARAMETER

DIGITALFILTERPERFORMANCE

PassbandStopbandPass-bandrippleStop-bandattenuation

DIGITALFILTERPERFORMANCE

GroupdelaytimeDe-emphasiserror

POWERSUPPLYREQUIREMENTSVCCVDD

Voltagerange

fS=48kHz/ADC,fS=48kHz/DACfS=96kHz/ADC,fS=96kHz/DAC

ICC

fS1=48kHz/ADC,fS2=192kHz/DACfS=48kHz/ADC,powerdown/DACPowerdown/ADC,fS=48kHz/DAC

Supplycurrent

Fullpowerdown

(12)(13)

TESTCONDITIONSSLOWROLLOFF

PCM3060PWMIN

TYP

MAX0.308

fS

0.73fS

UNIT

HzHz

<0.308fS>0.73fS

–35

20/fS±0.1

4.52.7

53.32525251213780916135515016018017077824.4

–25

105

±0.5dBdBsdB

5.53.630

VDCmAmAmAmAmAµA

fS=48kHz/ADC,fS=48kHz/DACfS=96kHz/ADC,fS=96kHz/DACfS1=48kHz/ADC,fS2=192kHz/DACfS=48kHz/ADC,powerdown/DACPowerdown/ADC,fS=48kHz/DACFullpowerdown(12)

fS=48kHz/ADC,fS=48kHz/DACfS=96kHz/ADC,fS=96kHz/DACfS1=48kHz/ADC,fS2=192kHz/DACfS=48kHz/ADC,powerdown/DACPowerdown/ADC,fS=48kHz/DACFullpowerdown(12)(13)

12mAmAmAmAmAµA

IDD

190

PowerdissipationmW

TEMPERATURERANGE

Operationtemperature

θJA

Thermalresistance

85

°C°C/W

(12)HaltSCKI1,SCKI2,BCK1,BCK2,LRCK1,LRCK2

(13)AC-coupledconfiguration.IfDC-coupledconfigurationisused,DCcurrentflowtoexternalloadisaddedanditdependsonexternalload

resistance.

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PINASSIGNMENTS

PCM3060

PW󰀀(TSSOP)󰀀PACKAGE

(TOPVIEW)

MC/SCL/FM/SDA/DEMPDOUTLRCK1BCK1SCKI1VDDDGNDSCKI2BCK2LRCK2DINZERORZEROL123456710111213142827262524232221201918171615MODE

MS/ADR/IFMDVINRVINLVCC

AGND1AGND2VCOMVOUTL+VOUTL–VOUTR+VOUTR–SGNDRSTP0043-03

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Table1.TERMINALFUNCTIONS

TERMINAL

NAMEAGND1AGND2BCK1BCK2DGNDDINDOUTLRCK1LRCK2MC/SCL/FM/SDA/DEMPMODEMS/ADR/IFMDRSTSCKI1SCKI2SGNDVCCVCOMVDDVINLVINRVOUTL–VOUTL+ZEROLZERORVOUTR–VOUTR+(1)(2)(3)(4)(5)

PIN23225108123411122827156916242172526192014131718

I/O––I/O(1)I/O(1)–I(2)OI/O(1)I/O(1)I(2)I/O(3)I

(4)

DESCRIPTION

ADCanaloggroundDACanalogground

Audiodatabitclockinput/outputforADCAudiodatabitclockinput/outputforDACDigitalground

AudiodatadigitalinputforDACAudiodatadigitaloutputforADC

Audiodataleft/rightclockinput/outputforADCAudiodataleft/rightclockinput/outputforDAC

Modecontrol,clockforSPI,clockforI2C,formatforH/Wmode(5)Modecontrol,dataforSPI,dataforI2C,de-emphasisforH/Wmode

Thispinprovidesfouroperationmodesaccordingtoitsinputconnection.ConnecteddirectlytoVDD:SPImode.ConnectedtoVDDthrough220-kΩpullupresistor:H/Wmode,single-endedVOUTX.ConnectedtoDGNDthrough220-kΩpulldownresistor:H/Wmode,differentialVOUTX.ConnecteddirectlytoDGND:I2Cmode.

Modecontrol,selectforSPIwithlowactive,addressforI2C,I/FmodeforH/WmodeResetandpower-downcontrolinput,active-lowSystemclockinputforADCSystemclockinputforDACShieldanalogground

ADC,DACanalogpowersupply,5-VADC,DACvoltagecommondecouplingDigitalpowersupply,3.3-VAnaloginputtoADC,L-channelAnaloginputtoADC,R-channel

AnalogoutputfromDAC,L-channel–indifferentialmode,mustbeopeninsingle-endedmodeAnalogoutputfromDAC,L-channel+indifferentialmode,L-channelinsingle-endedmodeZeroflag,L-channelZeroflag,R-channel

AnalogoutputfromDAC,R-channel–indifferentialmode,mustbeopeninsingle-endedmodeAnalogoutputfromDAC,R-channel+indifferentialmode,R-channelinsingle-endedmode

I(2)I

(5)

I(2)I(2)––––IIOOOOOO

Schmitt-triggerinput/outputwith50-kΩtypicalinternalpulldownresistorSchmitt-triggerinput,5-Vtolerant

Schmitt-triggerinput,5VtolerantforSPI,H/WmodeandSchmitt-triggerinput/opendrainLOWoutput,5-VtolerantforI2CVDD/2biased,quad-stateinput

Schmitt-triggerinputwith50-kΩtypicalinternalpulldownresistor,5-Vtolerant

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BLOCKDIAGRAM

VINLSEtoDiff.ConverterDelta-SigmaModulatorVDDDGNDDecimationFilterwithHPFVINRVCCAGND1SGNDAGND2VCOMZERORVOUTR–VOUTR+SEtoDiff.ConverterDelta-SigmaModulatorDOUTLRCK1CommonandReferenceVoltageCommonandReferenceAudioInterfaceandClockControlBCK1SCK1SCK2BCK2LRCK2LPFandBufferMulti-LevelDelta-SigmaModulatorInterpolationFilterwithDigitalFunctionDINRSTMODEModeControlMS/ADR/IFMDMC/SCL/FM/SDA/DEMPVOUTL+VOUTL–ZEROLLPFandBufferMulti-LevelDelta-SigmaModulatorB0229-01

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TYPICALPERFORMANCECURVESOFADCINTERNALFILTER

AllspecificationsatTA=25°C,VCC=5V,VDD=3.3V,fS=48kHz,SCKI1=SCKI2=512fS,24-bitdata,

unlessotherwisenoted.

DIGITALFILTER

DECIMATIONFILTER,STOP-BANDCHARACTERISTICS

0−20−40Amplitude − dBAmplitude − dB08162432G001

DECIMATIONFILTER,PASS-BANDCHARACTERISTICS

0.1

0.0

−60−80−100−120−140−160

Normalized Frequency [×fS]−0.1

−0.2

−0.3

−0.4

−0.5

0.00.10.20.30.40.5G002

Normalized Frequency [×fS]Figure1.Figure2.ANALOGFILTER

HIGH-PASSFILTERCHARACTERISTICS

0−5−10−15Amplitude − dB−20−25−30−35−40−45−50

0.00.10.20.30.4G003

ANTIALIASINGFILTERCHARACTERISTICS

0−5−10−15Amplitude − dB−20−25−30−35−40−45−501

10

100

f − Frequency − kHz

1k

10k

G004

Normalized Frequency [×fS/1000]Figure3.Figure4.

10

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TYPICALPERFORMANCECURVESOFDACINTERNALFILTER

AllspecificationsatTA=25°C,VCC=5V,VDD=3.3V,fS=48kHz,SCKI1=SCKI2=512fS,24-bitdata,

unlessotherwisenoted.

DIGITALFILTER

INTERPOLATIONFILTER,STOPBAND

(SHARP-ROLLOFF)

0−20−40Amplitude − dB−60−80−100−120−140−160

01234G005

INTERPOLATIONFILTER,PASSBAND

(SHARP-ROLLOFF)

0.1

0.0

Amplitude − dB−0.1

−0.2

−0.3

−0.4

−0.5

0.00.10.20.30.40.5G006

Normalized Frequency [×fS]Normalized Frequency [×fS]Figure5.Figure6.ANALOGFILTER

DE-EMPHASISFILTERCHARACTERISTICS

(fS=44.1kHz)

0−1−2−3

Amplitude − dB−4−5−6−7−8−9−10

0

2

4

6

8

10

12

14

16

18

20

G007

LOW-PASSFILTERCHARACTERISTICS

0

−10

Amplitude − dB−20

−30

−40

−50

110100f − Frequency − kHz1k10kG008f − Frequency − kHz

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TYPICALADCPERFORMANCECURVES

AllspecificationsatTA=25°C,VCC=5V,VDD=3.3V,fS=48kHz,SCKI1=SCKI2=512fS,24-bitdata,

unlessotherwisenoted.

THD+Nat–1dBvsTEMPERATURE

THD+N − Total Harmonic Distortion + Noise − dB−88VIN = –0.5 dB−90Dynamic Range and SNR − dB102104DYNAMICRANGEandSNRvsTEMPERATURE

−92100Dynamic Range−9498SNR−9696−94−100−25

0255075100

G009

92−25

0255075100

G010

TA − Free-Air Temperature − °CTA − Free-Air Temperature − °C

Figure9.

THD+Nat–1dBvsSUPPLYVOLTAGE

THD+N − Total Harmonic Distortion + Noise − dB−88VIN = –1 dB−90Dynamic Range and SNR − dB102104Figure10.

DYNAMICRANGEandSNRvsSUPPLYVOLTAGE

−92100Dynamic Range−9498SNR−9696−94−1004.50

4.755.005.255.50

G011

924.50

4.755.005.255.50

G012

VCC − Supply Voltage − VVCC − Supply Voltage − V

Figure11.Figure12.

12

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TYPICALDACPERFORMANCECURVES

AllspecificationsatTA=25°C,VCC=5V,VDD=3.3V,fS=48kHz,SCKI1=SCKI2=512fS,24-bitdata,

unlessotherwisenoted.

THD+NvsTEMPERATURE

THD+N − Total Harmonic Distortion + Noise − dB−90110DYNAMICRANGEandSNRvsTEMPERATURE

−92Dynamic Range and SNR − dB108−94106SNR−96104Dynamic Range102−98−100100−102−25

0255075100

G013

98−25

0255075100

G014

TA − Free-Air Temperature − °CTA − Free-Air Temperature − °C

Figure13.

THD+NvsSUPPLYVOLTAGE

THD+N − Total Harmonic Distortion + Noise − dB−90110Figure14.

DYNAMICRANGEandSNRvsSUPPLYVOLTAGE

−92Dynamic Range and SNR − dB108−94106SNR−96104Dynamic Range102−98−100100−1024.50

4.755.005.255.50

G015

984.50

4.755.005.255.50

G016

VCC − Supply Voltage − VVCC − Supply Voltage − V

Figure15.Figure16.

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TYPICALPERFORMANCECURVES

AllspecificationsatTA=25°C,VCC=5V,VDD=3.3V,fS=48kHz,SCKI1=SCKI2=512fS,24-bitdata,

unlessotherwisenoted.

ADCsOUTPUTSPECTRUM

OUTPUTSPECTRUM(–1dB,N=32768)

0−20−40Amplitude − dB−60−80−100−120−140

0

5

10

f − Frequency − kHz

15

20

G017

OUTPUTSPECTRUM(–60dB,N=32768)

0−20−40Amplitude − dB−60−80−100−120−140

0

5

10

f − Frequency − kHz

15

20

G018

Figure17.Figure18.

DACOUTPUTSPECTRUM

OUTPUTSPECTRUM(0dB,N=32768)

0−20−40Amplitude − dB−60−80−100−120−140

0

5

10

f − Frequency − kHz

15

20

G019

OUTPUTSPECTRUM(–60dB,N=32768)

0−20−40Amplitude − dB−60−80−100−120−140

0510f − Frequency − kHz

1520G020

Figure19.Figure20.

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PCM3060

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DEVICEDESCRIPTION

ASYNCHRONOUSOPERATION

ThePCM3060supportscompleteasynchronousoperationbetweentheADCandDACbyreceivingtwoindependentsystemclocksonSCKI1andSCKI2.

Also,thePCM3060supportssynchronousoperationbetweenADCandDACbyreceivingonecommonsystemclockoneitherSCKI1orSCKI2andcontrollingthesystemclockconfigurationthroughregister67or72inserialmodecontrol.

SYSTEMCLOCK

ThePCM3060requirestwosystemclocksforoperatingtheADCandDACblocksindependently,oritrequiresonecommonclockforsynchronousADCandDACoperation.

ThesystemclockfortheADCofthePCM3060mustbe256,384,512,or768fS,wherefSistheaudiosamplingratefortheADC,16to96kHz.

ThesystemclockfortheDACofthePCM3060mustbe128,192,256,384,512,or768fS,wherefSistheaudiosamplingratefortheDAC,16to192kHz.

Table2liststhetypicalsystemclockfrequencies,fSCKI1andfSCKI2forcommonaudiosamplingrates,andFigure21showsthetimingrequirementsforthesystemclockinputs.

Table2.SystemClockFrequenciesforCommonAudioSamplingClockFrequencies

SAMPLINGFREQUENCY

(kHz)

163244.14888.296176.4(1)192(1)

(1)(2)

SYSTEMCLOCKFREQUENCY,fSCKI1,fSCKI2[MHz]

128fS(1)2.0484.0965.886.14411.2612.28822.579224.576

192fS(1)3.0726.1448.46729.21616.934418.43233.868836.8

256fS4.0968.19211.2612.28822.579224.576See

(2)

384fS6.14412.28816.934418.43233.868836.8See(2)See(2)

512fS8.19216.38422.579224.576See(2)See(2)See(2)See(2)

768fS12.28824.57633.868836.8See(2)See(2)See(2)See(2)

See(2)

ThiscombinationofsamplingclockfrequencyandsystemclockfrequencyissupportedonlyfortheDAC.Thissystemclockfrequencyisnotsupportedforthegivensamplingclockfrequency.

tw(SCH)H

SystemClock(SCK1,󰀀SCK2)

L

tw(SCL)t(SCY)T0005-14

2V0.8VSYMBOLt(SCY)tw(SCH)tw(SCL)

PARAMETERSSystemclockcycletimeSystemclockhightimeSystemclocklowtimeSystemclockdutycycle

MIN250.4t(SCY)0.4t(SCY)40%

MAXUNITnsnsns

60%

Figure21.SystemClockInputTiming

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PCM3060

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POWER-ONRESETANDEXTERNALRESETSEQUENCE

ThePCM3060hasbothaninternalpower-onresetcircuitandanexternalresetcircuit.Thesequencesforbothresetsareshowninthefollowing.

Figure22illustratesthetimingoftheinternalpower-onreset.Initialization(reset)isdoneautomaticallyatthetimewhenVDDexceeds2.2Vtypical.

Internalresetisreleased1024SCKIx(x=1,2)afterpoweroniftheH/WcontrolmodeisselectedandRSTiskeptHIGH;thenthePCM3060beginsnormaloperation.IftheS/WcontrolmodeisselectedandRSTiskeptHIGH,internalresetisreleased1024SCKIxaftertheresetofADPSVandDAPSVthroughserialcontrolport;thenthePCM3060beginsnormaloperation.IfRSTiskeptLOW,internalresetisheldandtheresetsequenceisfrozenuntilRSTischangedfromLOWtoHIGH.VOUTLandVOUTRfromtheDACareforcedtotheVCOM(=0.5VCC)levelasVCCrises.IfsynchronizationismaintainedamongSCKIx,BCKx,andLRCKx,VOUTLandVOUTRgointothefade-insequenceaftertDACDLY1=2048/fSfrominternalresetrelease.ThenVOUTLandVOUTRprovideoutputscorrespondingtoDINaftertDACDLY2=1616/fSfromthestartoffade-in.Similarly,DOUTfromtheADCisenabledandgoesintothefade-insequenceaftertADCDLY1=2048/fSfrominternalresetrelease,andthenDOUTprovidesanoutputcorrespondingtoVINLandVINRaftertADCDLY2=1936/fSfromthestartoffade-in.Ifsynchronizationisnotheld,theinternalresetisnotreleasedandoperationmodeiskeptonresetandpower-downstate.Afterresynchronization,theDACbeginsitsfade-insequence,andtheADCalsobeginsfade-inoperationafterinternalinitializationandaninitialdelay.

Figure23isthetimingchartoftheexternalreset.TheRSTpininitiatesexternalforcedresetwhenRSTisheldLOWforatleasttRST=2048/fS;itresetsthedeviceplacesitinthepower-downstate,whichisthelowest-powerdissipationstateinthePCM3060.

WhenRSTtransitionsfromHIGHtoLOWwhileSCKIx,BCKx,andLRCKxaresynchronized,VOUTLandVOUTRareforcedtotheVCOM(=0.5VCC)levelafterthefade-outsequencelastingtDACDLY2=1616/fS,andDOUTisforcedtoZEROaftertADCDLY2=1936/fSfade-outsequence.Afterthat,theinternalresetbecomesLOW,thePCM3060resetsandentersintothepower-downstate,finallyallregistersandmemoryexceptmodecontrolregistersarereset.Toresumeintonormaloperation,changingRSTtoHIGHagainisrequired,andthesequenceshowninFigure22isperformed.ItispossibletohaltSCKIx,BCKxandLRCKxduringthepower-downstate,butallclocksmustberesumedpriortostartingthepower-upsequence.Thesamefade-in/-outsequenceofVOUTL/RandDOUTcanbeobtainedbysettingtheADPSVandDAPSVbitsthroughserialmodecontrolport.

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POWER-ONRESETANDEXTERNALRESETSEQUENCE(Continued)

(VDD=3.3󰀀Vtyp.)(VDD=2.7󰀀Vmin)

VDD

0V(VDD=2.2Vtyp.)SCKIx,BCKx,LRCKx

SynchronousClocksMODE

RSTADPSVDAPSV

(1)1024SCKIx1024SCKIxInternalReset

PowerDownt(DACDLY1)2048/fSNormalOperationt(DACDLY2)1616/fS0.5VCC

t(ADCDLY2)1936/fSFade-inT0097-02

VOUTL+/–VOUTR+/–

VCOM(0.5VCC)t(ADCDLY1)2048/fSDOUT

ZERONOTE:Releasefromthepower-savemodeisrequiredifthesoftwarecontrolmodeisselected.

Figure22.DACOutputandADCOutputforPower-OnReset

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PCM3060

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(VDD=3.3󰀀Vtyp.)

VDD

0V

SCKIx,BCKx,LRCKx

SynchronousClocksSynchronousClocksMODE

tRST2048/fSmin.RST2048/fSmin.ADPSVDAPSV

(1)1024SCKIxInternalReset

NormalOperationt(DACDLY2)1616/fSPowerDownNormalOperationt(DACDLY2)1616/fS0.5VCC

t(ADCDLY1)2048/fSt(ADCDLY2)1936/fSFade-inT0098-02

t(DACDLY1)2048/fSVOUTL+/–VOUTR+/–

t(ADCDLY2)1936/fSDOUT

Fade-outVCOM(0.5VCC)ZERO(1)

ADPSVandDAPSVcontrolVOUTL/RandDOUT,respectively,withfade-in/outthesameasforRST.Figure23.DACOutputandADCOutputforExternalReset

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PCMAUDIOINTERFACE

AudioInterfaceModeandTiming

Thedigitalaudiodatacanbeinterfacedineitherslaveormastermode,andthisinterfacemodeisselectableusingtheserialmodecontroldescribedintheModeControlsection.

TheinterfacemodeisalsoselectableindependentlyfortheADCandtheDAC.DINisalwaysinputtothePCM3060andDOUTisalwaysanoutputfromthePCM3060.SlavemodeisthedefaultmodeforboththeADCandtheDAC.

Inslavemode,BCK1/2andLRCK1/2areinputstothePCM3060,andBCK1/2mustbeeitherfSor48fS.DINissampledontherisingedgeofBCK2,andDOUTischangedonthefallingedgeofBCK1.ThedefaulttimingspecificationisshowninFigure24.

Inmastermode,BCK1/2andLRCK1/2areoutputsfromthePCM3060.BCK1/2andLRCK1/2aregeneratedbythePCM3060fromSCKI1/2,andBCK1/2isfixedatfS.DINissampledontherisingedgeofBCK2,andDOUTischangedonthefallingedgeofBCK1.ThedetailedtimingspecificationisshowninFigure25.

t(BCH)t(BCL)1.4V

t(BCY)t(LRH)BCK1/2(Input)

t(LRS)1.4V

LRCK1/2(Input)

t(DOD)DOUT

t(DIS)0.5VDD

t(DIH)1.4V

T0247-01

DIN

SYMBOLt(BCY)twtw

(BCH)(BCL)

DESCRIPTION

BCK1/2cycletimeBCK1/2hightimeBCK1/2lowtime

LRCK1/2set-uptimetoBCK1/2risingedgeLRCK1/2holdtimetoBCK1/2risingedgeDINsetuptimetoBCK1/2risingedgeDINholdtimetoBCK1/2risingedgeDOUTdelaytimefromBCK1/2fallingedge

MIN7535351010101015

TYPMAXUNITnsnsnsnsnsnsns

t(LRS)t(LRH)t(DIS)t(DIH)t(DOD)

70ns

NOTE:Loadcapacitanceofoutputis20pF.

Figure24.AudioDataInterfaceTiming(SlaveMode:BCK1/2andLRCK1/2WorkasInputs)

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SCKI1/2(Input)

t(BCH)t(BCD)1.4V

t(BCL)t(BCD)0.5VDD

BCK1/2(Output)

t(BCY)t(LRD)0.5VDD

LRCK1/2(Output)

t(DOD)DOUT

t(DIS)0.5VDD

t(DIH)1.4V

T0248-01

DIN

SYMBOLt(BCY)tw(BCH)tw(BCL)t(LRD)t(DIS)t(DIH)t(DOD)t(BCD)

(1)

BCK1/2cycletimeBCK1/2hightimeBCK1/2lowtime

PARAMETERSMIN1/fS0.4t(BCY)0.4t(BCY)

01010010

TYP0.5t(BCY)0.5t(BCY)

MAX0.6t(BCY)0.6t(BCY)

30

UNIT

LRCK1/2delaytimefromBCK1/2fallingedgeDINsetuptimetoBCK1/2risingedgeDINholdtimetoBCK1/2risingedgeDOUTdelaytimefromBCK1/2fallingedgeBCK1/2delaytimefromSCKI1/2risingedge(1)

nsnsns

3040

nsns

NOTE:Loadcapacitanceofoutputis20pF.

ThisspecificationappliesforSCKI1/2whenthefrequencyislessthan25MHz.

Figure25.AudioDataInterfaceTiming(MasterMode:BCK1/2andLRCK1/2workasOutputs)AudioInterfaceFormat

ThePCM3060supportsthefollowingfourinterfaceformatsinbothslaveandmastermodes,andtheyareselectableindependentlyfortheADCandDACusingserialmodecontrol.

24-bitI2Sformat

24-bitleft-justifiedformat24-bitright-justifiedformat16-bitright-justifiedformatAllformatsareprovidedinMSB-first,2scomplementdataformat.

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FMT1/2[1:0]󰀀=󰀀00

24-Bit,󰀀MSB-First,󰀀IS

LRCK1/2

Left-Channel

Right-Channel

2

BCK1/2

DIN123222324

LSB

123222324

LSB

MSB

DOUT

1

2

3

MSB1

2

3

222324

LSB

222324

LSB

MSBMSB

FMT1/2[1:0]󰀀=󰀀01

24-Bit,󰀀MSB-First,󰀀Left-Justified

LRCK1/2

Left-Channel

Right-Channel

BCK1/2

DIN123222324

LSB

123222324

LSB

1

MSB

DOUT

1

2

3

MSB1

2

3

222324

LSB

222324

LSB

1

MSBMSB

FMT1/2[1:0]󰀀=󰀀10

24-Bit,󰀀MSB-First,󰀀Right-Justified

LRCK1/2

Left-Channel

Right-Channel

BCK1/2

DIN24123222324

LSB

123222324

LSB

MSB

DOUT

24

1

2

3

MSB1

2

3

222324

LSB

222324

LSB

MSBMSB

FMT1/2[1:0]󰀀=󰀀11

16-Bit,󰀀MSB-First,󰀀Right-Justified

LRCK1/2

Left-Channel

Right-Channel

BCK1/2

DIN16123141516

LSB

123141516

LSB

MSB

DOUT

16

1

2

3

MSB1

2

3

141516

LSB

141516

LSB

T0016-18

MSBMSB

Figure26.AudioDataInput/OutputFormat

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PCM3060

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SYNCHRONIZATIONWITHDIGITALAUDIOSYSTEM

AsthePCM3060operatesunderthesystemclock(SCKI1/2)andtheaudiosamplingclock(LRCK1/2),SCKI1/2andLRCK1/2musthaveaspecificrelationshipinslavemode.ThePCM3060doesnotneedaspecificphaserelationshipbetweenaudiotheinterfaceclocks(LRCK1/2,BCK1/2)andsystemclock(SCKI1/2),butdoesrequireafrequencysynchronizationofLRCK1/2,BCK1/2,andSCKI1/2.

IftherelationshipbetweenSCKI2andLRCK2changesmorethan±6BCK2s(BCK2=fS)or±5BCK2s(BCK2=48fS)duetojitterorfrequencychange,etc.,internaloperationofDAChaltswithin2/fS,andanalogoutputisforcedtoVCOM(0.5VCC)untilresynchronizationofSCKI2toLRCK2andBCK2iscompletedandthentDACDLY3passesby.

IftherelationshipbetweenSCKI1andLRCK1changesmorethan±6BCK1s(BCK1=fS)or±5BCK1s(BCK1=48fS)duetojitter,frequencychange,etc.,internaloperationofADChaltswithin2/fS,anddigitaloutputisforcedintoZEROcodeuntilresynchronizationofSCKI1toLRCK1andBCK1iscompletedandthentADCDLY3passesby.

Incaseofchangeslessthan±5BCK1/2s(BCK1/2=)or±4BCK1/2s(BCK1/2=48),resynchronizationdoesnotoccur,andpreviouslydescribedanalog/digitaloutputcontrolanddiscontinuitydonotoccur.Figure27illustratestheDACanalogoutputandADCdigitaloutputforlossofsynchronization.

Duringundefineddata,itmaygeneratesomenoiseinaudiosignal.Also,thetransitionofnormaltoundefineddataandundefinedorzerodatatonormalcreatesadiscontinuityinthedataontheanaloganddigitaloutputs,whichmaygeneratesomenoiseintheaudiosignal.

TheADCoutput,DOUTandDACoutputs,andVOUTXholdthepreviousstateifthesystemclockhalts.

State󰀀of󰀀Synchronization

SynchronousAsynchronoust(DACDLY3)(22/fS)NormalSynchronousWithin󰀀2/fSDAC󰀀VOUTX+/–

NormalUndefinedDataVCOM(0.5󰀀VCC)t(ADCDLY3)(32/fS)ADC󰀀DOUT

NormalUndefinedDataZeroNormalT0020-08

Figure27.DACOutputandADCOutputforLossofSynchronization

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PCM3060

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ANALOGINPUTSTOADC

ThePCM3060hastwoindependentinputchannels,VINLandVINR.Thesearesingle-ended(unbalanced)inputs,eachcapableof0.6-VCCVppinputwith10-kΩinputresistance,typically.

ANALOGOUTPUTSFROMDAC

ThePCM3060hastwoindependentoutputchannels,VOUTLandVOUTR.Thesearedifferential,(balanced)outputs,eachcapableofdriving0.8-VCCVpp(1.6-Vppindifferential)typicalwitha10-kΩdc-coupledload.TheinternaloutputamplifiersforVOUTL+,VOUTL–andVOUTR+,VOUTR–arebiasedtoVCOM,describedasfollows.TheoutputamplifiersincludeanRCcontinuous-timefilter,whichhelpstoreducetheout-of-bandnoiseenergypresentattheDACoutputsduetothenoiseshapingcharacteristicsofthePCM3060delta-sigmamodulators.Thefrequencyresponseofthisfilterisshowninthetypicalperformancecurves.Thisfilterisnotenoughtoattenuatetheout-of-bandnoisetoanacceptablelevelformanyapplicationsingeneral.Anexternallow-passfilterisusediffurtherout-of-bandnoiserejectioninrequired.

VOUTX+,VOUTX–configurationcanbechangedtosingle-ended(unbalanced)outputviaaMODEpinsettingorserialmodecontrol,andVOUTX+isassignedasanoutputpininsingle-endedmode.

VCOMOUTPUT

Oneunbufferedcommonvoltageoutputpin,VCOM(pin20)isbroughtoutfordecouplingpurposes.Thispinisinternallybiasedtoadcvoltagelevelof0.5VCCnominal,andisusedasaninternalcommonvoltageandreferencevoltagefortheADCandDAC.Thispincanbeusedtobiasanexternalcircuit,buttheloadimpedancemustbehighenoughforoperationwiththeoutputresistanceofthispin,whichis12.5kΩ,typically.

OVERSAMPLINGRATECONTROL

Theove-samplingrateofADCofPCM3060isfixedatfS,buttheoversamplingrateofDACofPCM3060isoneoffS,32fSor16fS,andthisisautomaticallyselectedbytheratioofsystemclockfrequencyandsamplingfrequency.Anditcanbealsosettodoublerate,i.e.,oneof128fS,fSor32fS,throughserialcontrol.

ZEROFLAGS

Zero-DetectCondition

ForeachDACchannel,thePCM3060hasazero-detectcircuitthatrecognizeszerodetectionwhen1024consecutivezeroshavebeensampledonDIN.Zero-FlagOutputs

Therearetwozero-flagoutputs,ZEROLandZEROR.Thesepinscanbeusedtooperateexternalmutecircuits,orusedasstatusindicatorsforamicrocontroller,audiosignalprocessor,etc.ThesepinscanbeprogrammedinfollowingtwomodesusingtheserialcontrolportasdescribedintheMODECONTROLsection.

AZRO0(default)

1

DESCRIPTION

ZEROLL-chzerodetectionL-chandR-chzerodetection

ZERORR-chzerodetectionL-chandR-chzerodetection

Forzerodetection,thesepinsaresettoHIGH(1)bydefault,butthepolarityofthezero-flagoutputscanbeinvertedthroughtheserialcontrolport.

ZREV0(default)

1

DESCRIPTIONHIGHforzerodetectionLOWforzerodetection

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PCM3060

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MODECONTROL

ThePCM3060supportsthefollowingthreetypesofmodecontrolinterfaceandfourtypesofoperationconfiguration,accordingtotheinputstateofMODE(pin28)asfollows.Thepulluporpulldownresistormustbe220kΩ±5%.

MODETietoDGND

PulldownresistortoDGNDPullupresistortoVDD

TietoVDD

MODECONTROLINTERFACE

2-wire(I2C)serialcontrol,selectableVOUTXconfiguration

3-wireparallelcontrol,differentialVOUTX3-wireparallelcontrol,single-endedVOUTX

3-wire(SPI)serialcontrol,selectableVOUTXconfiguration

TheinputstateoftheMODEpinissampledduringpower-onresetorexternalreset;therefore,aninputchangeafterresetisignoreduntilthenextresetisperformed.

Thedefinitions(assignments)ofthefollowingthreepinsarechangedbythiscontrolmodesetting.

PIN2127

DEFINITION

SPIMDMCMSI2CSDASCLADR

H/WDEMPFMTIFMD

Inserialmodecontrol,theactualmodecontrolisperformedbyregisterwrite(andread)throughanSPI-orI2C-compatibleserialcontrolport.

Inparallelmodecontrol,threespecificfunctionsarecontrolleddirectlythroughhigh/lowsettingsofthreespecificpins.

PARALLELHARDWARECONTROL

IFMD(InterfaceMode)

LOWHIGH

DESCRIPTION

SlavemodeforADC,slavemodeforDACMaster(256fS)modeforADC,slavemodeforDAC

TheaudiointerfaceoftheADCandDACcanbeindependentfromeachother,butmodeselectionisappliedonboth.

FMT(InterfaceFormat)

LOWHIGH

DESCRIPTION24-bitI2SforADCandDAC24-bitleft-justifiedforADCandDAC

TheaudiointerfaceoftheADCandDACcanbeindependentfromeachother,butformatselectionisappliedonboth.

DEMP(De-emphasis)

LOWHIGH

(1)

The44.1-kHzde-emphasisfilterisalwaysselected.

DESCRIPTIONDe-emphasisoffDe-emphasison

(1)

3-WIRE(SPI)SERIALCONTROL

ThePCM3060supportsSPI-compatibleserialports,whichoperateasynchronouslytotheaudioserialinterface.ThecontrolinterfaceconsistsofMD,MC,andMS.MDistheserialdatainput,usedtoprogramthemodecontrolregisters.MCistheserialbitclock,usedtoshiftthedataintothecontrolport.MSistheselectinput,usedtoenablethemodecontrolport.

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RegisterWriteOperation

Allsingle-writeoperationsviatheserialcontrolportuse16-bitdatawords.Figure28showsthecontroldatawordformat.Themostsignificantbitmustbea0.Therearesevenbits,labeledIDX[6:0],thatsettheregisterindex(address)forthewriteoperation.Theleastsignificanteightbits,D[7:0],containthedatatobewrittentotheregisterspecifiedbyIDX[6:0].

Figure29showsthefunctionaltimingdiagramforsingle-writeoperationsontheserialcontrolport.MSisheldintheHighstateuntilaregisteristobewritten.Tostarttheregisterwritecycle,MSissettotheLowstate.SixteenclocksarethenprovidedonMC,correspondingtothe16bitsofthecontroldatawordonMD.Afterthesixteenthclockcyclehascompleted,MSissettoHightolatchthedataintotheindexedmodecontrolregister.

ThePCM3060supportsthemultiple-writeoperationinadditiontothesingle-writeoperation.MultiplewriteisperformedbysendingN-setsof8-bitregisterdataafterthefirst16bitsofregisteraddressandregisterdata,whilekeepingtheMCclockandMSintheLowstate.Closingthemultiple-writeoperationisdonebysettingMStotheHighstate.

MSB0

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0

D7

D6

D5

D4

D3

D2

D1

LSBD0

Register Index (or Address)Register Data

R0001-01

Figure28.ControlDataWordFormatforMD

MSMC

MDX0

IDX6IDX5IDX4IDX3IDX2IDX1IDX0

D7D6D5D4D3D2D1D0XX0

IDX6

T0048-01

Figure29.RegisterWriteOperation

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TimingRequirements

Figure30showsadetailedtimingdiagramforthe3-wireserialcontrolinterface.Thesetimingparametersarecriticalforpropercontrolportoperation.

t(MHH)MS1.4󰀀V

t(MSS)t(MCH)MC

t(MCL)t(MSH)1.4󰀀V

t(MCY)LSBMD

t(MDS)t(MDH)T0013-10

1.4󰀀V

SYMBOLt(MCY)tw(MCL)tw

(MCH)

PARAMETER

MCcycletimeMClow-leveltimeMChigh-leveltimeMShigh-leveltime

MSfallingedgetoMCrisingedge

MSrisingedgefromMCrisingedgeforLSB(1)MDholdtimeMDsetuptime

MIN1004040t(MCY)15151515

MAXUNITnsnsnsnsnsnsnsns

t(MHH)t(MSS)t(MSH)t(MDH)t(MDS)(1)

MCriseedgeforLSBtoMSriseedge.

Figure30.ControlInterfaceTimingforSPI

TWO-WIRE(I2C)SERIALCONTROL

ThePCM3060supportstheI2C-compatibleserialbusandthedatatransmissionprotocolforstandard-modeandfast-mode(CBmax=100pF)asaslavedevice.Thisprotocolisexplainedinthewell-knownI2C2.0specification.SlaveAddressMSB1

0

0

0

1

1

ADR

LSBR/W26

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ThePCM3060has7bitsforitsownslaveaddress.Thefirstsixbits(MSBs)oftheslaveaddressarefactorypresetto100011.Thenextbitoftheaddressbyteisthedeviceselectbit,whichcanbeuser-definedbytheADRpin(pin27).TwoPCM3060satmaximumcanbeconnectedonthesamebusatonetime.EachPCM3060respondswhenitreceivesitsownslaveaddress.PacketProtocol

Amasterdevicemustcontrolpacketprotocol,whichconsistsofastartcondition,slaveaddresswithread/writebit,dataifwriteoracknowledgementifread,andstopcondition.ThePCM3060supportstheslavereceiverfunction.

SDA

SCLSt1-7SlaveAddress8R/W9ACK1-8DATA9ACK1-8DATA9ACK9ACKSpStartCondition

R/W:󰀀󰀀󰀀Read󰀀Operation󰀀if󰀀1;󰀀Otherwise,󰀀Write󰀀OperationACK:Acknowledgement󰀀of󰀀a󰀀Byte󰀀if󰀀0,󰀀notAcknowledgement󰀀of󰀀a󰀀Byte󰀀if󰀀1DATA:󰀀󰀀󰀀8󰀀Bits󰀀(Byte)

StopCondition

T0049-06

WriteOperation

ThePCM3060supportsthereceiverfunction.AmastercanwritetoanyPCM3060registersusingsingleormultipleaccesses.ThemastersendsaPCM3060slaveaddresswithawritebit,aregisteraddress,andthedata.Ifmultipleaccessisrequired,theaddressisthatofthestartingregister,followedbythedatatobetransferred.Whenthedataarereceivedproperly,theindexregisterisincrementedby1automatically.Whentheindexregisterreaches4Ah,thenextvalueis40h.Whenundefinedregistersareaccessed,thePCM3060doesnotsendanacknowledgement.Figure31isadiagramofthewriteoperation.Theregisteraddressandthewritedataare8-bitinMSB-firstformat.

TransmitterDataType

MStMSlaveAddressMWSACKMRegAddressSACKMWrite󰀀Data󰀀1W:󰀀WriteSACKMWrite󰀀Data󰀀2SACKSACKMSpM:󰀀Master󰀀Device󰀀󰀀󰀀󰀀󰀀S:󰀀Slave󰀀Device󰀀󰀀󰀀󰀀󰀀St:󰀀Start󰀀ConditionACK:Acknowledgement󰀀󰀀󰀀󰀀󰀀Sp:󰀀Stop󰀀ConditionR0002-04

Figure31.FrameworkforWriteOperation

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TimingDiagram

ThedetailedtimingdiagramforSCLandSDAisshownasfollows.

Start

t(D-HD)t(BUF)t(D-SU)t(SDA-R)Repeated󰀀Start

t(SDA-F)t(P-SU)Stop

SDA

t(SCL-R)t(LOW)t(S-HD)t(GW)SCL

t(S-HD)t(SCL-F)T0050-04t(HI)t(S-SU)TimingCharacteristics

SYMBOLf(SCL)t(BUF)t(LOW)t(HI)t(S-SU)t(S-HD)t(D-SU)t(D-HD)t(SCL-R)t(SCL-F)t(SDA-R)t(SDA-F)t(P-SU)t(GW)CB

SCLclockfrequency

BusfreetimebetweenSTOPandSTARTconditionsLowperiodoftheSCLclockHighperiodoftheSCLclock

SetuptimeforSTART/repeatedSTARTconditionHoldtimeforSTART/repeatedSTARTconditionDatasetuptimeDataholdtimeRisetimeofSCLsignalFalltimeofSCLsignalRisetimeofSDAsignalFalltimeofSDAsignalSetuptimeforSTOPconditionAllowableglitchwidth

CapacitiveloadforSDAandSCLlines

Noisemarginathighlevelforeachconnecteddevice(includinghysteresis)Noisemarginatlowlevelforeachconnecteddevice(includinghysteresis)HysteresisofSchmitt-triggerinput

0.2VDD0.1VDDN/A4

N/A400

0.2VDD0.1VDD0.05VDD

4.74.744.742500

34501000100010001000

PARAMETER

STANDARDMODEMIN

MAX100

1.31.30.60.60.6100020+0.1CB20+0.1CB20+0.1CB20+0.1CB

0.6

50100900300300300300

FASTMODEMIN

MAX400

UNITkHzµsµsµsµsµsnsnsnsnsnsnsµsnspFVVV

Figure32.ControlInterfaceTimingforI2C

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MODECONTROLREGISTERS

ThePCM3060hasmanyuser-programmablefunctionswhichareaccessedviacontrolregisters,andtheyareprogrammedthroughtheSPIorI2Cserialcontrolport.Table3liststheavailablemodecontrolfunctionsalongwithresetdefaultconditionsandassociatedregisteraddresses.TheregistermapisshowninTable3.

Table3.User-ProgrammableModeControlFunctions

FUNCTIONRESET

Modecontrolregisterreset(ADCandDAC)Systemreset(ADCandDAC)ADCpower-savecontrol(ADC)DACpower-savecontrol(DAC)VOUTconfigurationcontrol(DAC)

Digitalattenuationcontrol,0dBto–100dBin0.5-dBsteps(DAC)

ClockselectforDACoperation(DAC)

Master/slavemodeforDACaudiointerface(DAC)InterfaceformatforDACaudiointerface(DAC)Oversamplingratecontrol(DAC)Outputphaseselect(DAC)Soft-mutecontrol(DAC)Digitalfilterrolloffcontrol(DAC)

De-emphasissamplingrateselection(DAC)De-emphasisfunctioncontrol(DAC)Zero-flagpolaritycontrol(DAC)Zero-flagformselect(DAC)

Digitalattenuationcontrol,20dBto–100dBin0.5-dBsteps(ADC)

ClockselectforADCoperation(ADC)

Master/slavemodeforADCaudiointerface(ADC)InterfaceformatforADCaudiointerface(ADC)

Zero-crossdetectiondisablefordigitalattenuationcontrol(ADC)HPFbypasscontrol(ADC)Inputphaseselect(ADC)Soft-mutecontrol(ADC)

DEFAULTNormaloperationNormaloperationPowersavePowersaveDifferential0dB,noattenuation

CLK2enable

SlaveI2S

Low(x/x32/x16)

NormalMutedisabledSharprolloff44.1kHzDe-emphasisdisabledHighfordetectionL-ch,R-chindependent0dB,noattenuation

CLK1enable

SlaveI2S

Zero-crossdetectionenabled

Bypassdisabled

NormalMutedisabled

REGISTER

65and66

676767686868696969696970and71

72727273737373

LABELMRSTSRSTADPSVDAPSVS/E

AT21[7:0],AT22[7:0]

CSEL2M/S2[2:0]FMT2[1:0]OVERDREV2MUT22,MUT21

FLTDMF[1:0]DMCZREVAZRO

AT11[7:0],AT12[7:0]

CSEL1M/S1[2:0]FMT1[1:0]ZCDDBYPDREV1MUT12,MUT11

Table4.RegisterMap

REGISTERADDRESS

HEX40h41h42h43h44h45h46h47h48h49h

DECRegisterRegister65Register66Register67Register68Register69Register70Register71Register72Register73

B150000000000

B141111111111

B130000000000

B120000000000

B110000000011

B100000111100

B90011001100

B80101010101

B7MRSTAT217AT227CSEL2RSV(1)FLTAT117AT127CSEL1RSV(1)

B6SRSTAT216AT226M/S22OVERDMF1AT116AT126M/S12RSV(1)

B5ADPSVAT215AT225M/S21RSV(1)DMF0AT115AT125M/S11RSV(1)

B4DAPSVAT214AT224M/S20RSV(1)DMCAT114AT124M/S10ZCDD

DATA

B3RSV(1)AT213AT223RSV(1)RSV(1)RSV(1)AT113AT123RSV(1)BYP

B2RSV(1)AT212AT222RSV(1)DREV2RSV(1)AT112AT122RSV(1)DREV1

B1RSV(1)AT211AT221FMT21MUT22ZREVAT111AT121FMT11MUT12

B0S/EAT210AT220FMT20MUT21AZROAT110AT120FMT10MUT11

(1)

RSVmeansreservedforfactoryuseorfutureextension,andthesebitsshouldbesetto0duringregularoperation.Donotwriteanyvaluesinaddressesotherthanthoselisted.

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REGISTERDEFINITIONS

B15

Register

0

B14

1

B13

0

B12

0

B11

0

B10

0

B9

0

B8

0

B7

MRST

B6

SRST

B5

ADPSV

B4

DAPSV

B3

RSV

B2

RSV

B1

RSV

B0

S/E

MRST:ModeControlRegisterReset(ADCandDAC)Defaultvalue:1

MRST=0MRST=1

Setdefaultvalue

Normaloperation(default)

TheMRSTbitcontrolsresetofthemodecontrolregisterstotheirdefaultvalues.Popnoisemaybegenerated.ReturningtheMRSTbitto1isnotrequired,astheMRSTbitisautomaticallysetto1afteramodecontrolregisterreset.

SRST:SystemReset(ADCandDAC)Defaultvalue:1

SRST=0SRST=1

ResynchronizationNormaloperation(default)

TheSRSTbitcontrolssystemreset,therelationbetweensystemclockandsamplingclockisre-synchronized,andADCoperationandDACoperationisrestarted.ThemodecontrolregisterisnotresetandthePCM3060doesnotgointopowerdownstate,butpop-noisemaybegenerated.ReturningtheSRSTbitto1isnotrequired,astheSRSTbitisautomaticallysetto1aftertriggeringasystemreset.ADPSV:ADCPower-SaveControl(ADC)Defaultvalue:1

ADPSV=0ADPSV=1

Normaloperation

Power-savemode(default)

TheADPSVbitcontrolstheADCpower-savemode.Inpower-savemode,DOUTisforcedtoZEROwithafade-outsequence,theinternalADCdataarereset,andtheADCgoesintothepower-downstate.Forpower-savemoderelease,afade-insequenceisappliedonDOUTduringtheresumeprocess.Theserialmodecontrolisenabledduringthismode.Awaitingtimeofmorethan2048/fSisrequiredfortheproperstatuschangebythispowersavecontrolon/off.Asthedefaultstateafterpoweronisthepower-savemodeandDOUTisdisabled(ZERO),releasefromthepower-savemodeisrequiredfornormaloperation.ThedetailedsequenceandtimingforADPSVcontrolisshownFigure22andFigure23.

NOTE:

Itisrecommendedthatchanging/stoppingclocksorchangingtheaudiointerfacemodebeperformedinpower-downmodeinordertoavoidunexpectedpop/clicknoiseandperformancedegradation.

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DAPSV:DACPower-SaveControl(DAC)Defaultvalue:1

DAPSV=0DAPSV=1

Normaloperation

Power-savemode(default)

TheDAPSVbitcontrolsDACpower-savemode.Inpower-savemode,DACoutputsareforcedtoVcomwithafade-outsequence,theinternalDACdataareresetandtheDACgoesintothepower-downstate.Forpower-savemoderelease,afade-insequenceisappliedontheDACoutputsinresumeprocess.Theserialmodecontrolisenabledduringthismode.Awaitingtimeofmorethan2048/fSisrequiredfortheproperstatuschangebythispower-savecontrolon/off.Asthedefaultstateafterpoweronisthepower-savemodeandtheDACoutputsaredisabled(VCOM),releasefromthepower-savemodeisrequiredfornormaloperation.ThedetailedsequenceandtimingforDAPSVcontrolisshownFigure22andFigure23.

NOTE:

Itisrecommendedthatchanging/stoppingclocksorchangingtheaudiointerfacemodebeperformedinpower-downmodeinordertoavoidunexpectedpop/clicknoiseandperformancedegradation.

S/E:DACOutputConfigurationControl(DAC)Defaultvalue:0

S/E=0S/E=1

Differential(default)Single-ended

TheS/EbitallowstheusertoselecttheconfigurationoftheDACoutputontheVOUTXpinsaccordingtoapplicationcircuit.

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B15

Register65

0

B14

1

B13

0

B12

0

B11

0

B10

0

B9

0

B8

1

B7

AT217

B6

AT216

B5

AT215

B4

AT214

B3

AT213

B2

AT212

B1

AT211

B0

AT210

B15

Register66

0

B14

1

B13

0

B12

0

B11

0

B10

0

B9

1

B8

0

B7

AT227

B6

AT226

B5

AT225

B4

AT224

B3

AT223

B2

AT222

B1

AT221

B0

AT220

AT2x[7:0]:DigitalAttenuationLevelSetting(DAC)

Wherex=1or2,correspondingtotheDACoutputVOUTL(x=1)andVOUTR(x=2).Defaultvalue:11111111b

AT2x[7:0]11111111b11111110b11111101b

:10000001b10000000b01111111b

:00111000b00110111b00110110b

:00000000b

DECIMALVALUE

255254253:129128127:565554:0

ATTENUATIONLEVELSETTING0dB,noattenuation(default)–0.5dB–1dB:–63dB–63.5dB–dB:–99.5dB–100dBMute:Mute

EachDACchannel(VOUTLandVOUTR)hasadigitalattenuatorfunction.Theattenuationlevelmaybesetfrom0dBto–100dBin0.5-dBsteps,andalsomaybesettoinfiniteattenuation(mute).Theattenuationlevelchangefromcurrentvaluetotargetvalueisperformedbyincrementingordecrementingone0.5-dBstepforevery8/fStimeinterval.Whiletheattenuationlevelchangesequenceisinprogress,newcommandsforattenuationlevelchangearenotprocessed,butthenewcommandoverwritesthepreviouscommandinthecommandbuffer.Thelastcommandforattenuationlevelchangeisperformedafterthepresentattenuationlevelchangesequenceisfinished.

Theattenuationlevelforeachchannelcanbesetindividuallyusingthefollowingformula,andtheforegoingtableshowsattenuationlevelsforvarioussettings:

Attenuationlevel(dB)=0.5×(AT2x[7:0]DEC–255),whereAT2x[7:0]DEC=0through255forAT2x[7:0]DEC=0through54,thelevelissettoinfiniteattenuation(mute).

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B15

Register67

0

B14

1

B13

0

B12

0

B11

0

B10

0

B9

1

B8

1

B7

CSEL2

B6

M/S22

B5

M/S21

B4

M/S20

B3

RSV

B2

RSV

B1

FMT21

B0

FMT20

CSEL2:ClockSelectforDACOperation

Defaultvalue:0(SCKI2,BCK2,LRCK2enabledforDACoperation)

CSEL2=0CSEL2=1

SCKI2,BCK2,LRCK2enabledforDACoperation(default)SCKI1,BCK1,LRCK1enabledforDACoperation

TheCSEL2bitcontrolssystemclockandaudiointerfaceclocksfortheDACoperation.

SCKI2,BCK2,LRCK2areusedfortheDACportionifCSEL2=0(default),andSCKI1,BCK1,LRCK1areusedforDACoperationifCSEL2=1.

M/S2[2:0]:AudioInterfaceModeforDACDefaultvalue:000(slavemode)

M/S2[2:0]000001010011100101110111

AudioInterfaceModeforDACSlavemode(default)Mastermode,768fSMastermode,512fSMastermode,384fSMastermode,256fSMastermode,192fSMastermode,128fSReserved

TheM/S2[2:0]bitscontroltheaudiointerfacemodefortheDAC.FMT2[1:0]:AudioInterfaceFormatforDACDefaultvalue:00(I2SMode)

FMT2[1:0]

00011011

AudioInterfaceFormatforDAC24-bitI2Sformat(default)24-bitleft-justifiedformat24-bitright-justifiedformat16-bitright-justifiedformat

TheFMT2[1:0]bitscontroltheaudiointerfaceformatfortheDAC.

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B15

Register68

0

B14

1

B13

0

B12

0

B11

0

B10

1

B9

0

B8

0

B7

RSV

B6

OVER

B5

RSV

B4

RSV

B3

RSV

B2

DREV2

B1

MUT22

B0

MUT21

OVER:OversamplingRateControl(DAC)Defaultvalue:0

OVEROVER=0OVER=1

Systemclock=512fSor768fS×Oversampling(default)×128Oversampling

Systemclock=256fSor384fS×32Oversampling(default)×Oversampling

Systemclock=128fSor192fS×16Oversampling(default)×32Oversampling

TheOVERbitisusedtocontroltheoversamplingrateofthedelta-sigmaD/Aconverters.

SettingOVER=1mightimproveout-of-bandnoisecharacteristicsinsomeapplicationenvironments,butitmightalsoslightlyaffectbasebandperformance.

Writingoverthisbitduringnormaloperationmaygeneratepopnoise.DREV2:OutputPhaseSelect(DAC)Defaultvalue:0

DREV2=0DREV2=1

Normaloutput(default)Invertedoutput

TheDREV2bitisusedtocontrolthephaseoftheanalogsignaloutputs(VOUTLandVOUTR).MUT2x:SoftMuteControl(DAC)

wherex=1or2,correspondingtotheDACoutputVOUTL(x=1)andVOUTR(x=2).Defaultvalue:0

MUT2x=0MUT2x=1

Mutedisabled(default)Muteenabled

Themutebits,MUT21andMUT22,areusedtoenableordisablethesoftmutefunctionforthecorrespondingDACoutputs,VOUTLandVOUTR.Thesoftmutefunctionisincorporatedintothedigitalattenuators.Whenmuteisdisabled(MUT2x=0),theattenuatorandDACoperatenormally.WhenmuteisenabledbysettingMUT2x=1,thedigitalattenuatorforthecorrespondingoutputisdecreasedfromthecurrentsettingtoinfiniteattenuationattherateofone0.5-dBstepforevery8/fStimeinterval.BysettingMUT2x=0,theattenuatorisincreasedtothepreviouslyprogrammedattenuationlevelattherateofone0.5-dBstepforevery8/fStimeinterval.Thisprovidespop-freemutingoftheDACoutput.

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B15

Register69

0

B14

1

B13

0

B12

0

B11

0

B10

1

B9

0

B8

1

B7

FLT

B6

DMF1

B5

DMF0

B4

DMC

B3

RSV

B2

RSV

B1

ZREV

B0

AZRO

FLT:DigitalFilterRolloffControl(DAC)Defaultvalue:0

FLT=0FLT=1

Sharprolloff(Default)Slowrolloff

TheFLTbitallowstheusertoselectthedigitalfilterroll-offthatisbestsuitedtotheirapplication.SharpandSlowfilterroll-offselectionsareavailable.ThefilterresponsesfortheseselectionsareshownintheTypicalPerformanceCurvessectionofthisdatasheet.

DMF[1:0]:SamplingFrequencySelectionfortheDe-EmphasisFunction(DAC)Defaultvalue:00

DMF[1:0]00011011

De-EmphasisSamplingRateSelection44.1kHz(default)48kHz32kHzReserved

TheDMF[1:0]bitsareusedtoselectthesamplingfrequencyofthedigitalde-emphasisfunctionwhenitisenabled.

DMC:DigitalDe-EmphasisFunctionControl(DAC)Defaultvalue:0

DMC=0DMC=1

De-emphasisdisabled(default)De-emphasisenabled

TheDMCbitisusedtoenableordisablethedigitalde-emphasisfunction.SeetheplotsshownintheTypicalPerformanceCurvessectionofthisdatasheetforfrequencycharacteristics.ZREV:Zero-FlagPolaritySelect(DAC)Defaultvalue:0

ZREV=0ZREV=1

Highforzerodetect(default)Lowforzerodetect

TheZREVbitisusedtocontrolthepolarityofzeroflagpins.AZRO:Zero-FlagFunctionSelect(DAC)Defaultvalue:0

AZRO=0AZRO=1

ZEROL:L-chZEROdetection(default)ZEROL:LandRZEROdetection

ZEROR:R-chZEROdetection(default)ZEROR:LandRZEROdetection

TheAZRObitisusedtoselectthefunctionofzeroflagpins.

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B15

Register70

0

B14

1

B13

0

B12

0

B11

0

B10

1

B9

1

B8

0

B7

AT117

B6

AT116

B5

AT115

B4

AT114

B3

AT113

B2

AT112

B1

AT111

B0

AT110

B15

Register71

0

B14

1

B13

0

B12

0

B11

0

B10

1

B9

1

B8

1

B7

AT127

B6

AT126

B5

AT125

B4

AT124

B3

AT123

B2

AT122

B1

AT121

B0

AT120

AT1x[7:0]:DigitalAttenuationLevelSetting(ADC)

wherex=1or2,correspondingtotheADCoutputL-chpartofDOUT(x=1)orR-chpartofDOUT(x=2).Defaultvalue:11010111b

AT1x[7:0]11111111b11111110b11111101b

:11011000b11010111b11010110b

:00010000b00001111b00001110b

:00000000b

DECIMALVALUE

255254253:216215214:161514:0

ATTENUATIONLEVELSETTING20dB19.5dB19dB:0.5dB

0dB,noattenuation(default)–0.5dB:–99.5dB–100dBMute:Mute

EachADCchannelhasadigitalattenuatorfunctionwith20-dBgain.Theattenuationlevelmaybesetfrom20dBto–100dBin0.5-dBsteps,andalsomaybesettoinfiniteattenuation(mute).Theattenuationlevelchangefromthecurrentvaluetothetargetvalueisperformedbyincrementingordecrementingoneby0.5-dBstepatthetimingofzero-crossdetectionontheinputsignalwhichissampledforevery1/fStimeinterval,orforevery8/fStimeintervalifthezero-crossdetectionmodeisdisabledbyZCDDsetting.Ifazero-crossingisnotdetectedfor512/fS,actuallevelchangeisdoneforevery1/fStimeintervaluntilazero-crossingisdetectedagain.Whiletheattenuationlevelchangesequenceisinprogress,newcommandsforattenuationlevelchangearenotprocessed,butthenewcommandoverwritesthepreviouscommandinthecommandbuffer.Thelastcommandforattenuationlevelchangeisperformedafterthepresentattenuationlevelchangesequenceisfinished.Theattenuationlevelforeachchannelcanbesetindividuallyusingthefollowingformula,andtheabovetableshowsattenuationlevelsforvarioussettings:

Attenuationlevel(dB)=0.5×(AT1x[7:0]DEC–215),whereAT1x[7:0]DEC=0through255forAT1x[7:0]DEC=0through14,thelevelissettoinfiniteattenuation(mute).

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B15

Register72

0

B14

1

B13

0

B12

0

B11

1

B10

0

B9

0

B8

0

B7

CSEL1

B6

M/S12

B5

M/S11

B4

M/S10

B3

RSV

B2

RSV

B1

FMT11

B0

FMT10

CSEL1:ClockSelectforADCOperation

Defaultvalue:0(SCKI1,BCK1,LRCK1enabledforADCoperation)

CSEL1=0CSEL1=1

SCKI1,BCK1,LRCK1enabledforADCoperation(default)SCKI2,BCK2,LRCK2enabledforADCoperation

TheCSEL1bitcontrolsthesystemclockandaudiointerfaceclocksfortheADCoperation.

SCKI1,BCK1,LRCK1areusedforADCportionifCSEL1=0(default),andSCKI2,BCK2,LRCK2areusedforADCportionifCSEL1=1.

M/S1[2:0]:AudioInterfaceModeforADCDefaultvalue:000(slavemode)

M/S1[2:0]000001010011100101110111

AudioInterfaceModeforADCSlavemode(default)Mastermode,768fSMastermode,512fSMastermode,384fSMastermode,256fSReservedReservedReserved

TheM/S1[2:0]bitscontroltheaudiointerfacemodefortheADC.FMT1[1:0]:AudioInterfaceFormatforADCDefaultvalue:00(I2Smode)

FMT1[1:0]

00011011

AudioInterfaceFormatforADC24-bitI2Sformat(default)24-bitleft-justifiedformat24-bitright-justifiedformat16-bitright-justifiedformat

TheFMT1[1:0]bitscontroltheaudiointerfacemodeforADC.

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B15

Register73

0

B14

1

B13

0

B12

0

B11

1

B10

0

B9

0

B8

1

B7

RSV

B6

RSV

B5

RSV

B4

ZCDD

B3

BYP

B2

DREV1

B1

MUT12

B0

MUT11

ZCDD:Zero-CrossDetectionDisableforDigitalAttenuation(ADC)Defaultvalue:0

ZCDD=0ZCDD=1

Zero-crossdetectionenabled(default)Zero-crossdetectiondisabled

TheZCDDbitcontrolsthezero-crossdetectfunctionfordigitalattenuationandmute.Whenzero-crossdetectionisenabled,theactuallevelchangefordigitalattenuationandmuteisdoneatthetimingofzero-crossdetectionontheinputsignalwhichissampledforevery1/fStimeinterval.Ifzero-crossingisnotdetectedfor512/fS,theactuallevelchangeisdoneforevery1/fStimeintervaluntilazero-crossingisdetectedagainastimeoutcontrolfornozero-crossinginputsignal.Whenzero-crossdetectionisdisabled,theactuallevelchangeisdoneatthetimingof8/fStimeinterval.BYP:HPFBypassControl(ADC)Defaultvalue:0

BYP=0BYP=1

Normaloutput,HPFenabled(default)Bypassedoutput,HPFdisabled

TheBYPbitcontrolstheHPFfunction;thedccomponentoftheinputsignalandtheinternaldcoffsetareconvertedinbypassmode.

DREV1:InputPhaseSelect(ADC)Defaultvalue:0

DREV1=0DREV1=1

Normalinput(default)Invertedinput

TheDREV1bitisusedtocontrolthephaseofanalogsignalinputs(VINLandVINR).MUT1x:SoftMuteControl(ADC)

wherex=1or2,correspondingtotheADCoutputL-chpartofDOUT(x=1)andR-chpartofDOUT(x=2).Defaultvalue:0

MUT1x=0MUT1x=1

Mutedisabled(default)Muteenabled

Themutebits,MUT11andMUT12,areusedtoenableordisablethesoftmutefunctionforthecorrespondingADCoutputs,DOUT.Thesoftmutefunctionisincorporatedintothedigitalattenuators.Whenmuteisdisabled(MUT1x=0),theattenuatorandADCoperatenormally.WhenmuteisenabledbysettingMUT1x=1,thedigitalattenuatorforthecorrespondingoutputisdecreasedfromthecurrentsettingtoinfiniteattenuationin0.5dBstepatthetimingofzero-crossdetectionontheinputsignalwhichissampledforevery1/fStimeinterval,orforevery8/fStimeintervalifzero-crossdetectionmodeisdisabledbyZCDDsetting.Ifazero-crossingisnotdetectedfor512/fS,actuallevelchangeisdoneforevery1/fStimeintervaluntilzero-crossingisdetectedagain.BysettingMUT1x=0,theattenuatorisincreasedtothepreviouslyprogrammedattenuationlevelin0.5dBstepinthesamemannerasfordecreasing.Thisprovidespop-freemutingfortheADCinput.

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TYPICALCIRCUITCONNECTION

Figure33illustratestypicalcircuitconnection.

ControlMCU123AudioReceiver/Encoder456C23.3󰀀V0V7AudioTransmitter/Decoder1011121314MC/FMT/SCLMODE282726AnalogInputLRCK1BCK1SCKI1VDDDGNDSCKI2BCK2LRCK2DINZERORZEROLVINLVCCAGND1AGND2VCOMVOUTL+VOUTL–VOUTR+VOUTR–SGNDRST25C424C1232221C3201918171615Analog󰀀OutputPost󰀀LPFandBuffer0󰀀V5󰀀VC5TerminationMD/DEMP/SDAMS/IFMD/ADRDOUTVINRNote:C1,C2:󰀀0.1-mF󰀀ceramic󰀀capacitor󰀀and󰀀10-mF󰀀electrolytic󰀀capacitor,󰀀depend󰀀on󰀀power󰀀supply.

C3:󰀀0.1-mF󰀀ceramic󰀀capacitor󰀀and󰀀10-mF󰀀electrolytic󰀀capacitor󰀀is󰀀recommended.C4,󰀀C5:󰀀4.7-mF󰀀electrolytic󰀀capacitor󰀀is󰀀recommended󰀀for󰀀3-Hz󰀀cutoff󰀀frequency.The󰀀termination󰀀for󰀀mode/configuration󰀀control.

Either󰀀one󰀀of󰀀following󰀀circuits󰀀has󰀀to󰀀be󰀀applied󰀀according󰀀to󰀀necessary󰀀mode/configuration.Resistor󰀀value󰀀must󰀀be󰀀220󰀀kW,±5%󰀀tolerance.

3.3V3.3V282828(1)28(2)(3)0V(4)0VS0257-01

Figure33.TypicalApplicationDiagram

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PCM3060

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ApplicationExamplesforAnalogInputandOutput

a)ExampleofVCOMbiasedbufferingfor2Vrmsinputwithovervoltageprotection.

R2C2C1InputR1R3VINX–VVCOMC3+VExampleofC,R󰀀valueR1:20󰀀kWR2:11kWR3:1󰀀kWC1:10mFC2:220󰀀pFC3:0.1mFfc:66kHz

b)Exampleofcapacitor-lessdifferentialtosingle-endedconverterwithLPFandgainfor2Vrmsstandardoutput.

R3

ExampleofC,R󰀀value

C2R1VOUTX+C1VOUTX–R2R4C3R6–VR5R7Output+V

R1,󰀀R2:10󰀀kWR3,󰀀R4:7.5kWR5,󰀀R6:1.8󰀀kWR7:󰀀100WC1:1000󰀀pFC2,󰀀C3:470󰀀pFfc:kHz

c)ExampleofVCOM-biasedsinglesupplysingle-endedapplicationwithLPFandMUTEcontrolfor2Vrmsstandardoutput.

R2C2R1R3+VC4MuteOutputExampleofC,R󰀀valueR1:10󰀀kWR2:15kWR3:2.4󰀀kWC1:1500󰀀pFC2:220󰀀pFC3:0.1mFC4:󰀀10mFfc:57kHz

VOUTX+VCOMC1C3ZEROxORMuteS0258-01

Figure34.ApplicationExamplesforAnalogInputandOutput

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DESIGNANDLAYOUTCONSIDERATIONSINAPPLICTION

PowerSupplyPins(VCC,VDD)

ThedigitalandanalogpowersupplylinestothePCM3060shouldbebypassedtothecorrespondinggroundpinswith0.1-µFceramicand10-µFelectrolyticcapacitorsasclosetothepinsaspossibletomaximizethedynamicperformanceoftheADCandDAC.

AlthoughthePCM3060hastwopowerlinestomaximizethepotentialofdynamicperformance,usingonecommonsource,5-VpowersupplyforVCCanda3.3-VpowersupplyforVDDwhichisgeneratedfromthe5-VpowersupplyforVCC,isrecommendedtoavoidunexpectedproblems,suchaslatch-up,fromincorrectpowersupplysequencing.

Grounding(AGND1,AGND2,SGND,DGND)

TomaximizethedynamicperformanceofthePCM3060,theanaloganddigitalgroundsarenotconnectedinternally.Thesepointsshouldhaveverylowimpedancetoavoiddigitalnoiseandsignalcomponentsfeedingbackintotheanalogground.So,theyshouldbeconnecteddirectlytoeachotherunderthepartstoreducethepotentialofnoiseproblems.VINL,VINRPins

A4.7-µFelectrolyticcapacitorisrecommendedastheaccouplingcapacitor,whichgivesa3-Hzcutofffrequency.Ifhigherfull-scaleinputvoltageisrequired,itcanbeadjustedbyaddingonlyoneseriesresistortotheVINXpins,althoughasmallgainerrorisaddedduetovariationsofabsoluteinputresistanceofthePCM3060.Forexample,adding9.1kΩgives2Vrmsfull-scalewithabout10%gainerror.VCOMPin

Ceramic0.1-µFandelectrolytic10-µFcapacitorsarerecommendedbetweenVCOMandAGNDtoensurelowsourceimpedanceoftheADCandDACreferences.ThesecapacitorsshouldbelocatedascloseaspossibletotheVCOMpinstoreducedynamicerrorsonADCandDACreferences.VOUTL+,VOUTL–,VOUTR+,VOUTR–Pins

Thedifferentialtosingle-endedbufferwithpostLPFcanbedirectly(withoutcapacitor)connectedtotheseoutputpins,therebyminimizingtheuseofcouplingcapacitorsforthe2-Vrmsoutputs.Theoutputpinsinsingle-endedmodeareassignedtoVOUTL+andVOUTR+;insingle-endedmode,theVOUTL–andVOUTR–pinsmustbeopen.MODEPin

Thispinisalogicinputwithquad-stateinputcapability.

ThepinisconnectedtoVDDforHigh,toDGNDforLow,andpulleduporpulleddownthroughanexternalresistorandforthetwomid-statesinordertodistinguishthefourinputstates.Thepulluporpulldownresistormustbe220kΩ,±5%tolerance.SystemClocks

ThequalityofSCKI1/2mayinfluencedynamicperformance,asthePCM3060(bothADCandDAC)operatesbasedonSCKI1/2.Therefore,itmayberequiredtoconsiderthejitter,duty,riseandfalltime,etc.ofthesystemclocks.

ThePCM3060supportsasynchronousoperationbetweentheADCandDAC.Therefore,thereisnorestrictionontherelationshipbetweenSCKI1andSCKI2fordigitaloperation,butitisstronglyrecommendedtouseacommonclockiftheapplicationdoesnotrequiredifferentbaseclockfrequencies,like44.1kHzand48kHz.

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AudioInterfaceClocks

Inslavemode,PCM3060doesnotrequirespecifictimingrelationshipbetweenBCK1/LRCK1andSCKI1,BCK2/LRCK2andSCKI2,butthereisapossibilityofperformancedegradationwithacertaintimingrelationshipbetweenthem.Inthatcase,specifictiming-relationshipcontrolmightsolvethisperformancedegradation.Inmastermode,thereisapossibilityofperformancedegradationduetoheavyloadsonBCK1/LRCK1,BCK2/LRCK2andDOUT.Itisrecommendedtoloadthesepinsaslightlyaspossible.ExternalMuteControl

Forpower-downON/OFFcontrolwithoutthepopnoisewhichisgeneratedbyadclevelchangeontheDACoutput,theexternalmutecontrolisgenerallyrequired.Useofthefollowingcontrolsequenceisrecommended:externalmuteON,codecpowerdownON,SCKI1/SCKI2stopandresumeifnecessary,codecpowerdownOFF,andexternalmuteOFF.

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PACKAGEOPTIONADDENDUM

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30-Mar-2007

PACKAGINGINFORMATION

OrderableDevicePCM3060PWPCM3060PWR

(1)

Status(1)ACTIVEACTIVE

PackageTypeTSSOPTSSOP

PackageDrawingPWPW

PinsPackageEcoPlan(2)

Qty2828

502000

TBDTBD

Lead/BallFinish

CallTICallTI

MSLPeakTemp(3)CallTICallTI

Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.

LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.

NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.

PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.

(2)

EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.

Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.

Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.

Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)

(3)

MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.

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