ADL5310资料

FEATURES

2 independent channels optimized for photodiode interfacing

6-decade input dynamic range

Law conformance 0.3 dB from 3 nA to 3 mA Temperature-stable logarithmic outputs

Nominal slope 10 mV/dB (200 mV/dec), externally scalable Intercepts may be independently set by external resistors User-configurable output buffer amplifiers Single- or dual-supply operation

Space-efficient, 24-lead 4 mm × 4 mm LFCSP Low power: < 10 mA quiescent current

APPLICATIONS

Gain and absorbance measurements Multichannel power monitoring

General-purpose baseband log compression

PRODUCT DESCRIPTION

The ADL53101 low cost, dual logarithmic amplifier converts input current over a wide dynamic range to a linear-in-dB output voltage. It is optimized to determine the optical power in wide-ranging optical communication system applications, including control circuitry for lasers, optical switches, atten-uators, and amplifiers, as well as system monitoring. The device is equivalent to a dual AD8305 with enhanced dynamic range (120 dB). While the ADL5310 contains two independent signal channels with individually configurable transfer function

constants (slope and intercept), internal bias circuitry is shared between channels for improved power consumption and

channel matching. Dual converters in a single, compact LFCSP package yield space-efficient solutions for measuring gain or attenuation across optical elements. Only a single supply is

required; optional dual-supply operation offers added flexibility. The ADL5310 employs an optimized translinear structure that use the accurate logarithmic relationship between a bipolar transistor’s base emitter voltage and collector current, with appropriate scaling by precision currents to compensate for the inherent temperature dependence. Input and reference current pins sink current ranging from 3 nA to 3 mA (limited to ±60 dB between input and reference) into a fixed voltage defined by the VSUM potential. The VSUM potential is internally set to

500 mV but may be externally grounded for dual-supply opera-tion, and for additional applications requiring voltage inputs.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

120 dB Range (3 nA to 3 mA) Dual Logarithmic ConverterADL5310FUNCTIONAL BLOCK DIAGRAM

665kΩVREFVRDZVSUMOUT1COMMVOUT1Ωk99IRF1.4SCL1VBIAS6.69kΩBIN1VNEGTEMPERATUREILOGCOMPENSATION451ΩLOG114.2kΩIPD1INP1OUT20.5V2.5VREFERENCE20kΩ80kΩGENERATORVOUT2Ωk9IRF2COMM9.4VSCL2BIAS14.2kΩBIN2VNEGTEMPERATUREILOGCOMPENSATION451ΩLOG26.69kΩIPD2INP2VSUMCOMM100-0-5665kΩ1VREF440

Figure 1.

The logarithmic slope is set to 10 mV/dB (200 mV/decade) nominal and can be modified using external resistors and the independent buffer amplifiers. The logarithmic intercepts for each channel are defined by the individual reference currents, which are set to 3 μA nominal for maximum input range by connecting 665 kΩ resistors between the 2.5 V VREF pins and the IRF1 and IRF2 inputs. Tying VRDZ to VREF effectively sets the x-intercept four decades below the reference current—typically 300 pA for a 3 µA reference.

The use of individually optimized reference currents may be valuable when using the ADL5310 for gain or absorbance measurements where each channel input has a different current-range requirement. The reference current inputs

are also fully functional dynamic inputs, allowing log ratio operation with the reference input current as the denominator. The ADL5310 is specified for operation from –40°C to +85°C.

1

US Patents: 4,604,532, 5,519,308. Other patents pending.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com Fax: 781.326.8703© 2004 Analog Devices, Inc. All rights reserved.

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ADL5310

TABLE OF CONTENTS

Specifications.....................................................................................3 Absolute Maximum Ratings............................................................4 Pin Configuration and Function Descriptions.............................5 Typical Performance Characteristics.............................................6 General Structure............................................................................11 Theory..........................................................................................11 Managing Intercept and Slope..................................................12 Response Time and Noise Considerations..............................12

Applications.....................................................................................13 Calibration...................................................................................14 Minimizing Crosstalk................................................................14 Relative and Absolute Power Measurements..........................15 Characterization Methods.........................................................16 Evaluation Board............................................................................17 Outline Dimensions.......................................................................20 Ordering Guide...........................................................................20

REVISION HISTORY

9/04—Data Sheet Changed from Rev. 0 to Rev. A

Changes to Ordering Guide..........................................................20 11/03—Revision 0: Initial Version

Rev. A | Page 2 of 20

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ADL5310SPECIFICATIONS

VP = 5 V, VN = 0 V, TA = 25°C, RREF = 665 kΩ, and VRDZ connected to VREF, unless otherwise noted. Table 1.

Parameter Conditions INPUT INTERFACE Pins 1 to 6: INP1 and INP2, IRF1 and IRF2, VSUM Specified Current Range, IPDFlows toward INP1 pin or INP2 pin Input Current Min/Max Limits Flows toward INP1 pin or INP2 pin Reference Current, IREF, Range Flows toward IRF1 pin or IRF2 pin Summing Node Voltage Internally preset; user alterable Temperature Drift –40°C < TA < +85°C Input Offset Voltage VIN − VSUM, VIREF − VSUMLOGARITHMIC OUTPUTS Logarithmic Slope

Logarithmic Intercept1

Law Conformance Error

Wideband Noise2

Small Signal Bandwidth Maximum Output Voltage Minimum Output Voltage Output Resistance REFERENCE OUTPUT Voltage wrt Ground

Maximum Output Current

Incremental Output Resistance OUTPUT BUFFERS

Min Typ Max Unit 3 n 3 m A 10 m A 3 n 3 m A 0.46 0.5 0.54 V 0.030 mV/°C

+20 mV −20

Input Offset Voltage

Input Bias Current

Incremental Input Resistance Incremental Output Resistance Output High Voltage

Output Low Voltage

Peak Source/Sink Current Small-Signal Bandwidth Slew Rate POWER SUPPLY

Positive Supply Voltage Quiescent Current

Negative Supply Voltage (Optional)

Pin 15 and Pin 16: LOG1 and LOG2 190 200 210 mV/dec –40°C < TA < +85°C 185 215 mV/dec

165 300 535 pA –40°C < TA < +85°C 40 1940 pA 10 nA < IPD < 1 mA 0.1 0.4 dB 3 nA < IPD < 3 mA 0.3 0.6 dB IPD > 3 µA; output referred 0.5 µV/√Hz IPD = 3 µA 1.5 MHz 1.7 V Limited by VN = 0 V 0.10 V 4.375 5 5.625 kΩ Pin 7 and Pin 24 (internally shorted): VREF 2.45 2.5 2.55 V –40°C < TA < +85°C 2.42 2.58 V Sourcing (grounded load) 20 mA Load current < 10 mA 4 Ω Pins 12 to 14 and 17 to 19: OUT2, SCL2, BIN2, BIN1, SCL1, and OUT1 −20 +20 mV Flowing out of Pins 13, 14, 17, and 18 0.4 µA 35 MΩ Load current < 10 mA; gain = 1 0.5 Ω RL = 1 kΩ to ground V VP −

0.1

RL = 1 kΩ to ground 0.10 V 30 mA Gain = 1 15 MHz 0.2 V to 4.8 V output swing 15 V/µs Pins 8 and 9: VPOS; Pins 10, 11, and 20: VNEG (VP – VN ) ≤ 12 V 3 5 12 V Input currents < 10 µA 9.5 11.5 mA (VP – VN ) ≤ 12 V 0 V −5.5

12

Other values of logarithmic intercept can be achieved by adjustment of RREF.

Output noise and incremental bandwidth are functions of input current; measured using output buffer connected for GAIN = 1.

Rev. A | Page 3 of 20

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ADL5310

ABSOLUTE MAXIMUM RATINGS

Table 2.

Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress 12 V Supply Voltage VP − VN

Input Current

Internal Power Dissipation θJA

Maximum Junction Temperature 20 mA 500 mW 35°C/W1125°C

rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect Operating Temperature Range –40°C to +85°C device reliability.

Storage Temperature Range

−65°C to +150°C Lead Temperature Range (Soldering 60 sec)

300°C

1

With paddle soldered down.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 4 of 20

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ADL5310PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

COMMCOMMVNEG20VRDZVREF24232221VSUM1INP12IRF13IRF24INP25VSUM6OUT119PIN 1INDICATOR1817SCL1BIN1LOG1LOG2BIN2SCL2ADL5310DUAL LOG AMPTOP VIEW(Not to Scale)16151413VPOSVPOSVREFVNEGVNEGOUT204415-0-0027101112

Figure 2. 24-Lead LFCSP Pin Configuration

Table 3. Pin Function Descriptions

Pin No. 1, 6 2 3 4 5 7, 24 8, 9

10, 11, 20 12 13 14 15 16 17 18 19 21, 22 23

Mnemonic VSUM INP1 IRF1 IRF2 INP2 VREF VPOS VNEG OUT2 SCL2 BIN2 LOG2 LOG1 BIN1 SCL1 OUT1 COMM VRDZ

Function

Guard Pin. Used to shield the INP1 and INP2 input current lines, and for optional adjustment of the input summing node potentials. Pin 1 and Pin 6 are internally shorted.

Channel 1 Numerator Input. Accepts (sinks) photodiode current IPD1. Usually connected to photodiode anode such that photocurrent flows into INP1.

Channel 1 Denominator Input. Accepts (sinks) reference current, IRF1. Channel 2 Denominator Input. Accepts (sinks) reference current, IRF2.

Channel 2 Numerator Input. Accepts (sinks) photodiode current IPD2. Usually connected to photodiode anode such that photocurrent flows into INP2.

Reference Output Voltage of 2.5 V. Pin 7 and Pin 24 are internally shorted. Positive Supply, (VP – VN) ≤ 12 V. Both pins must be connected externally.

Optional Negative Supply, VN. These pins are usually grounded. For more details, see the General Structure and Applications sections. All VNEG pins must be connected externally. Buffer Output for Channel 2.

Buffer Amplifier Inverting Input for Channel 2. Buffer Amplifier Noninverting Input for Channel 2. Output of the Logarithmic Front End for Channel 2. Output of the Logarithmic Front End for Channel 1. Buffer Amplifier Noninverting Input for Channel 1. Buffer Amplifier Inverting Input for Channel 1. Buffer Output for Channel 1.

Analog Ground. Pin 21 and Pin 22 are internally shorted.

Intercept Shift Reference Input. The top of a resistive divider network that offsets VLOG to position the intercept. Normally connected to VREF; may also be connected to ground when bipolar outputs are to be provided.

Rev. A | Page 5 of 20

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ADL5310

TYPICAL PERFORMANCE CHARACTERISTICS

VP = 5 V, VN = 0 V, RREF = 665 kΩ, TA = 25°C, unless otherwise noted.

1.6T1.4VA =–40°C, 0°C, +25°C, +70°C,+85°CIN = 0V1.2)1.0(V GOL0.8V0.60.40.201n10n100n1µ10µ100µ1m10mIINP (A)Figure 3. VLOG vs. IINP for Multiple Temperatures

1.8TA =–40°C, 0°C, +25°C, +70°C,+85°C1.6VIN = 0V1.41.2)(V G1.0OLV0.80.60.40.201n10n100n1µ10µ100µ1m10mIREF (A)Figure 4. VLOG vs. IREF for Multiple Temperatures (IINP = 3 µA)

1.81.61.43µA300nA1.230nA)V1.03nA( GOLV0.80.63mA300µA0.430µA0.201n10n100n1µ10µ100µ1m10mIINP (A)Figure 5. VLOG vs. IINP for Multiple Values of IREF,

Decade Steps from 3 nA to 3 mA

2.01.5)1.0+85°C)B+70°Cd+25°C/Vm0.50(1 B0d( RO–0.5RR0°CE–40°C–1.0–1.53–2.0601n10n100n1µ10µ100µ1m10m000--00--551144440

IINP (A)0

Figure 6. Law Conformance Error vs. IINP for Multiple Temperatures,

Normalized to 25°C

2.01.51.0))B+70°C+85°Cd/Vm0.5+25°C0(1 B0d( RO–0.5RRE–1.0–40°C0°C–1.54–2.0701n10n100n1µ10µ100µ1m10m000--00--551144440

IREF (A)0

Figure 7. Law Conformance Error vs. IREF for Multiple Temperatures,

Normalized to 25°C (IINP = 3 µA)

1.00.83mA0.6300µA30µA))B0.4d/3µAVm0.20(1 B0d( R–0.2300nARORE–0.4–0.6–0.83nA30nA50–1.080-01n10n100n1µ10µ100µ1m10m00--0-515414404

IINP (A)0Figure 8. Law Conformance Error vs. IINP for Multiple Values of IREF,

Decade Steps from 3 nA to 3 mA

Rev. A | Page 6 of 20

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1.81.61.41.2VLOG (V)1.00.80.63nA30nA300nAADL531030µA300µA3mAERROR (dB (10mV/dB))0.43µA0.20–0.2–0.4–0.6–0.830µA3mA300µA3mA3µA1.00.83nA0.60.40.230nA300nA3µA04415-0-0091n10n100n1µ10µ100µ1m10m10n100n1µ10µ100µ1m10mIREF (A)

IREF (A)04415-0-01204415-0-01304415-0-0140–1.01n

Figure 9. VLOG vs. IREF for Multiple Values of IINP,

Decade Steps from 3 nA to 3 mA

Figure 12. Law Conformance Error vs. IREF for Multiple Values of IINP,

Decade Steps from 3 nA to 3 mA

2.0TA = 25°C1.51.00.8+5V, 0V0.6+12V, 0VERROR (dB (10mV/dB))0.40.2+9V, 0V+3V, 0VERROR (dB (10mV/dB))+12V, 0V1.00.50–0.5–1.0–1.5MEAN– 3σMEAN + 3σ0–0.2–0.4–0.6–0.810n100n1µ10µ100µ1m10m04415-0-010+5V,–5V+5V,–5V–1.01n–2.01n10n100n1µ10µ100µ1m10mIINP (A)

IPD (A)

Figure 10. Law Conformance Error vs. IINP for Various Supply Conditions

2.0TA = 0°C, 70°C1.51.00.50–0.5–1.0–1.504415-0-011Figure 13. Law Conformance Error Distribution (3σ to Either Side of Mean)

4TA =–40°C, 85°C3MEAN + 3σ AT–40°CERROR (dB (10mV/dB))MEAN + 3σ AT 70°CERROR (dB (10mV/dB))210–1–2–3–41nMEAN– 3σ AT–40°CMEAN + 3σ AT +85°CMEAN± 3σ AT 0°CMEAN– 3σ AT 70°C–2.01n10n100n1µ10µ100µ1m10m10n100n1µ10µ100µ1m10mIPD (A)

IPD (A)

Figure 11. Law Conformance Error Distribution (3σ to Either Side of Mean) Figure 14. Law Conformance Error Distribution (3σ to Either Side of Mean)

Rev. A | Page 7 of 20

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ADL5310

151053nA30µA30nA300nA1.4T-RISE < 1µs T-FALL < 1µs1.2T-RISE < 1µs T-FALL < 1µs30µA TO 300µA3µA TO 30µA300nA TO 3µA30nA TO 300nA3nA TO 30nA1.0T-RISE < 1µs T-FALL < 5µs0.8T-RISE < 5µs T-FALL < 10µs0.6T-RISE < 10µs T-FALL < 40µs0.40.204415-0-0151.6NORMALIZED RESPONSE (dB)0–5300µA TO 3mA–15–20–25–30–35–40–451k10k100k1M10M3mA3µA300µAVOUT (V)–10T-RISE < 30µs T-FALL < 80µs100M020406080100120140160180200FREQUENCY (Hz)

TIME (µs)04415-0-01804415-0-01904415-0-020–501000

Figure 15. Small Signal AC Response, IINP to VOUT (AV = 1) (5% Sine Modulation, Decade Steps from 3 nA to 3 mA)

1510530nA300nA3mA1.61.4Figure 18. Pulse Response—IINP to VOUT (AV = 1)

in Consecutive 1-Decade Steps

NORMALIZED RESPONSE (dB)0–5–10–15–20–25–30–35–40–451k10k100k1M10M100M04415-0-016T-RISE < 80µs T-FALL < 30µs1.23nA TO 30nA30nA TO 300nA300nA TO 3µA3µA TO 30µA30µA TO 300µA300µA TO 3mA3nA300µAVOUT (V)T-RISE < 40µs T-FALL < 10µs1.0T-RISE < 10µs T-FALL < 5µs0.8T-RISE < 1µs T-FALL < 1µs0.6T-RISE < 1µs T-FALL < 1µs0.4T-RISE < 1µs T-FALL < 1µs0.200204060801001203µA30µA–50100140160180200FREQUENCY (Hz)

TIME (µs)

Figure 16. Small Signal AC Response, IREF to VOUT (AV = 1) (5% Sine Modulation, Decade Steps from 3 nA to 3 mA)

1005.0Figure 19. Pulse Response—IREF to VOUT (AV = 1)

in Consecutive 1-Decade Steps

3nA1030nAµV rms/ Hz4.03.01300nA3µAmVrms2.00.11.0300µA0.011003mA30µA1k10k100k1M10M04415-0-01701n10n100n1µ10µ100µ1m10mFREQUENCY (Hz)

IINP (A)

Figure 17. Spot Noise Spectral Density at VOUT vs. Frequency (AV = 1)

for IINP in Decade Steps from 3 nA to 3 mA

Figure 20. Total Wideband Noise Voltage at VOUT vs. IINP (AV = 1)

Rev. A | Page 8 of 20

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ADL5310

255204153102)MEAN + 3σ)mVmV1MEAN + 3σ(5( TTFF0I0IRRDD –1MEAN– 3σF–5TREMEAN– 3σNPVIV–2–10–3–15–4–20–5–251–6–40–30–20–10010203040506070809020-0–40–30–20–100102030405060708090-5TEMPERATURE (°C)1440

TEMPERATURE (°C)Figure 21. VREF Drift vs. Temperature (3σ to Either Side of Mean)

Figure 24. VINPT Drift vs. Temperature (3σ to Either Side of Mean)

Normalized to 25°C

Normalized to 25°C

675534))c2MEAN + 3σc3eedd//MEAN + 3σV1V2mm(( 1 T0TFFII0RD–1RD –1YV–2MEAN– 3σY∆V–2MEAN– 3σ–3–3–4–4–5–5–62–6–40–30–20–10010203040506070809020-0–40–30–20–100102030405060708090-5TEMPERATURE (°C)1440

TEMPERATURE (°C)Figure 22. Slope Drift vs. Temperature (3σ to Either Side of Mean)

Figure 25. Slope Mismatch Drift vs. Temperature Normalized to 25°C

(VY1 – VY2, 3σ to Either Side of Mean) Normalized to 25°C

200200150150100100)AMEAN + 3σ)50MEAN + 3σp50A( pT( FTI0RFID0R ZD IZI–50MEAN– 3σ∆–50MEAN– 3σ–100–100–150–1503–40–30–20–102–20001020304050607080900-0–40–30–20–100102030405060708090-5TEMPERATURE (°C)1440

TEMPERATURE (°C)Figure 23. Intercept Drift vs. Temperature Figure 26. Intercept Mismatch Drift vs. Temperature (3σ to Either Side of Mean) Normalized to 25°C (IZ1 – IZ2, 3σ to Either Side of Mean) Normalized to 25°C

Rev. A | Page 9 of 20

420-0-51440

520-0-51440

620-0-51440

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ADL5310

700600500T400NUCO3002001000190195200205210SLOPE (mV/dec)Figure 27. Distribution of Logarithmic Slope

600500400TNU300CO2001000100200300400500INTERCEPT (pA)Figure 28. Distribution of Logarithmic Intercept

700600500T400NUCO30020010002.462.482.502.522.54VREF VOLTAGE (V)Figure 29. Distribution of VREF (RL = 100 kΩ)

450400350300TN250UCO200150100507002–9–6–30369300--00--55114

SLOPE MISMATCH (mV/dec)44400Figure 30. Distribution of Channel-to-Channel Slope Mismatch (VY1 – VY2)

500400300TNUCO2001008120300--0–300–200–10001002003000--551144440

INTERCEPT MISMATCH (pA)0Figure 31. Distribution of Channel-to-Channel Intercept Mismatch (IZ1 – IZ2)

500400300TNUCO2001009022300--–9–6–3036900--551144440

VINPT– VSUM VOLTAGE (mV)0Figure 32. Distribution of Offset Voltage (VINPT – VSUM)

Rev. A | Page 10 of 20

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ADL5310THEORY

The base-emitter voltage of a bipolar junction transistor (BJT) can be expressed by Equation 1, which immediately shows its basic logarithmic nature:

where:

IC is the collector current.

IS is a scaling current, typically only 10–17 A.

kT/q is the thermal voltage, proportional to absolute temperature (PTAT), and is 25.85 mV at 300 K.

IS is never precisely defined and exhibits an even stronger tem-perature dependence, varying by a factor of roughly a billion between −35°C and +85°C. Thus, to make use of the BJT as an accurate logarithmic element, both of these temperature dependencies must be eliminated.

The difference between the base-emitter voltages of a matched pair of BJTs, one operating at the photodiode current IPD and the other operating at a reference current IREF, can be written as

GENERAL STRUCTURE

The ADL5310 addresses a wide variety of interfacing conditions to meet the needs of fiber optic supervisory systems and is useful in many nonoptical applications. These notes explain the structure of this unique style of translinear log amp. Figure 33 shows the key elements of one of the two identical on-board log amps.

BIASGENERATORPHOTODIODE2.5VINPUTCURRENT80kΩIPDINP1(INP2)0.5VVSUMIREFVREFIREF20kΩCOMM0.5V14.2kΩVRDZ0.5VQ1VBE1Q2VBE26.69kΩCOMM04415-0-033VBE = kT/q ln(IC/IS) (1)

VBE1VBE2TEMPERATURECOMPENSATION(SUBTRACT ANDDIVIDE BY T°K)44µA/dec451ΩVLOGVNEG (NORMALLY GROUNDED)Figure 33. Simplified Schematic of Single Log Amp

The photodiode current IPD is received at either Pin INP1 or Pin INP2. The voltages at these nodes are approximately equal to the voltage on the adjacent guard pins, VSUM, as well as reference inputs IRF1 and IRF2, due to the low offset voltage of the JFET operational amplifiers. Transistor Q1 converts IPD to a corresponding logarithmic voltage, as shown in Equation 1. A finite positive value of VSUM is needed to bias the collector of Q1 for the usual case of a single-supply voltage. This is inter-nally set to 0.5 V, one-fifth of the 2.5 V reference voltage that appears on Pin VREF. Both VREF pins are internally shorted, as are both VSUM pins. The resistance at the VSUM pin is nominally 16 kΩ; this voltage is not intended as a general bias source.

The ADL5310 also supports the use of an optional negative supply voltage, VN, at Pin VNEG. When VN is 0.5 V or more negative, VSUM may be connected to ground; thus, INP1, INP2, IRF1, and IRF2 assume this potential. This allows operation as a voltage-input logarithmic converter by the inclusion of a series resistor at either or both inputs. Note that the resistor setting IREF for each channel needs to be adjusted to maintain the intercept value. Also note that the collector-emitter voltages of Q1 and Q2 are the full VN and effects due to self-heating cause errors at large input currents.

The input-dependent VBE1 of Q1 is compared with the reference VBE2 of a second transistor, Q2, operating at IREF. IREF is gener-ated externally to a recommended value of 3 µA. However, other values over a several-decade range can be used with a slight degradation in law conformance.

VBE1 – VBE2 = kT/q ln(IPD/IS) – kT/q ln(IREF/IS)

= ln(10) kT/q log10(IPD/IREF) (2) = 59.5 mV log10(IPD/IREF) (T = 300 K)

The uncertain, temperature-dependent saturation current, IS, that appears in Equation 1 has therefore been eliminated. To eliminate the temperature variation of kT/q, this difference voltage is processed by what is essentially an analog divider. Effectively, it puts a variable under Equation 2. The output of this process, which also involves a conversion from voltage mode to current mode, is an intermediate, temperature-corrected current:

where IY is an accurate, temperature-stable scaling current that determines the slope of the function (change in current per decade). For the ADL5310, IY is 44 µA, resulting in a

temperature-independent slope of 44 µA/decade for all values of IPD and IREF. This current is subsequently converted back to a voltage-mode output, VLOG, scaled 200 mV/decade.

It is apparent that this output should be 0 for IPD = IREF and would need to swing negative for smaller values of input current. To avoid this, IREF would need to be as small as the smallest value of IPD. Accordingly, an offset voltage is added to VLOG to shift it upward by 0.8 V when VRDZ is directly

connected to VREF. This moves the intercept to the left by four decades (at 200 mV/decade), from 3 μA to 300 pA:

where IINTC is the operational value of the intercept current. Because values of IPD < IINTC result in a negative VLOG, a negative supply of sufficient value is required to accommodate this situation.

ILOG = IY log10(IPD/IREF) (3)

ILOG = IY log10(IPD/IINTC) (4)

Rev. A | Page 11 of 20

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ADL5310

The voltage VLOG is generated by applying ILOG to an internal resistance of 4.55 kΩ, formed by the parallel combination of a 6.69 kΩ resistor to ground and a 14.2 kΩ resistor to Pin VRDZ (typically tied to the 2.5 V reference, VREF). At the LOG1 (LOG2) pin, the output current ILOG generates a voltage of

VLOG = ILOG × 4.55 kΩ

= 44 µA × 4.55 kΩ × log10(IPD/IINTC) (5) = VY log10(IPD/IINTC)

where VY = 200 mV/decade or 10 mV/dB. Note that any resis-tive loading on LOG1 (LOG2) lowers this slope and results in an overall scaling uncertainty. This is due to the variability of the on-chip resistors compared to the off-chip load. As a con-sequence, this practice is not recommended.

VLOG may also swing below ground when dual supplies (VP and VN) are used. When VN = −0.5 V or larger, the input Pins INP1 (INP2) and IRF1 (INP2) may be positioned at ground level simply by grounding VSUM. Care must be taken to limit the power consumed by the input BJT devices when using a larger negative supply, because self-heating degrades the accuracy at higher currents.

Thus, the effective intercept current IINTC is only one ten-thousandth of IREF, corresponding to 300 pA when using the recommended value of IREF = 3 µA.

The slope can be reduced by attaching a resistor between the log amp output pin, LOG1 or LOG2, and ground. This is strongly discouraged given that the on-chip resistors do not ratio

correctly to the added resistance. Also, it is rare that one would wish to lower the basic slope of 10 mV/dB; if this is needed, it should be effected at the low impedance output of the buffer amps, which are provided to avoid such miscalibration and to allow higher slopes to be used.

Each of the ADL5310’s buffers is essentially an uncommitted operational amplifier with rail-to-rail output swing, good load-driving capabilities, and a typical unity-gain bandwidth of 15 MHz. In addition to allowing the introduction of gain, using standard feedback networks and thereby increasing the slope voltage VY, the buffer can be used to implement multipole, low-pass filters, threshold detectors, and a variety of other functions. Further details on these applications can be found in the AD8304 data sheet.

MANAGING INTERCEPT AND SLOPE

When using a single supply, VRDZ should be directly connected to VREF to allow operation over the entire 6-decade input current range. As noted in the Theory section, this introduces an accurate offset voltage of 0.8 V at the LOG1 and LOG2 pins, equivalent to four decades, resulting in a logarithmic transfer function that can be written as

VLOG = VY log10(104 × IPD/IREF)

(6) = VY log10(IPD/IINTC) where IINTC = IREF/104.

RESPONSE TIME AND NOISE CONSIDERATIONS

The response time and output noise of the ADL5310 are funda-mentally a function of the signal current, IPD. For small currents,

the bandwidth is proportional to IPD, as shown in Figure 15. The output low frequency voltage-noise spectral-density is a function of IPD (see Figure 17) and also increases for small values of IREF. Details of the noise and bandwidth performance of translinear log amps can be found in the AD8304 data sheet.

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ADL53105VVREFVRDZVPOSCOMMIRF1IRF1SCL12kΩ4.7nFVBIASVNEG6.69kΩITEMPERATURELOGCOMPENSATION14.2kΩIPD11kΩ1nF20kΩCOMMIRF22kΩ4.7nFVBIASIRF26.69kΩIPD21kΩ1nF1nF665kΩINP2VSUMCOMM04415-0-034APPLICATIONS

665kΩVSUMOUT1IPD10.5log101nAVOUT112kΩ( )8kΩBIN1LOG1451ΩCFLT110 nFINP1OUT20.5V80kΩ2.5VREFERENCEGENERATORVOUT212kΩSCL2IPD20.5log101nA( )8kΩ14.2kΩITEMPERATURELOGCOMPENSATIONBIN2LOG2451ΩCFLT210 nFVNEGVREFVNEGCOMM

Figure 34. Basic Connections for Fixed Intercept Use

The ADL5310 is easy to use in optical supervisory systems and in similar situations where a wide-ranging current is to be converted to its logarithmic equivalent—that is, represented in decibel terms. Basic connections for measuring a single current at each input are shown in Figure 34, which also

includes various nonessential components, as explained next. The 2 V difference in voltage between the VREF and Input Pins INP1 and INP2, in conjunction with the external 665 kΩ resis-tors RRF1 and RRF2, provides 3 µA reference currents IRF1 and IRF2 into Pins IRF1 and IRF2. Connecting VRDZ to VREF raises the voltage at LOG1 and LOG2 by 0.8 V, effectively lowering each intercept current IINTC by a factor of 104 to position it at 300 pA. A wide range of other values for IREF, from 3 nA to 3 mA, may be used. The effect of such changes is shown in Figure 5 and Figure 8.

Any temperature variation in RRF1 (RRF2) must be taken into account when estimating the stability of the intercept. Also, the overall noise increases when using very low values of IRF1 (IRF2). In fixed-intercept applications there is little benefit in using a large reference current, because doing so only compresses the low-current-end of the dynamic range when operated from a single supply. The capacitor between VSUM and ground is

strongly recommended to minimize the noise on this node, to reduce channel-to-channel crosstalk, and to help provide clean reference currents.

In addition, each input and reference pin (INP1, INP2, IRF1, and IRF2) has a compensation network made up of a series resistor and capacitor. The junction capacitance of the photo-diode along with the network capacitance of the board artwork around the input system creates a pole that varies widely with input current. The RC network stabilizes the system by simul-taneously reducing this pole frequency and inserting a zero to compensate an additional pole inherent in the input system. In general, the 1 nF, 1 kΩ network handles almost any photodiode interface. In situations where larger active area photodiodes are used, or when long input traces are used, the capacitor value may need to be increased to ensure stability. Although the signal and reference input systems are similar, additional care is required to ensure stable operation of the reference inputs at temperature extremes across the full current range of IRF1 (IRF2). It is recommended that filter components of 4.7 nF and 2 kΩ should be used from Pin IRF1 (IRF2) to ground. Temperature-stable components should always be used in critical locations such as the compensation networks; Y5V-type chip capacitors are to be avoided due to their poor temperature stability.

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ADL5310

The optional capacitor from LOG1 (LOG2) to ground forms a single-pole, low-pass filter in combination with the 5 kΩ resis-tance at this pin. For example, when using a CFLT of 10 nF, the 3 dB corner frequency is 3.2 kHz. Such filtering is useful in minimizing the output noise, particularly when IPD is small. Multipole filters are more effective in reducing the total noise; examples are provided in the AD8304 data sheet.

Because the basic scaling at LOG1 (LOG2) is 0.2 V/decade, and thus a 4 V swing at the buffer output would correspond to 20 decades, it is often useful to raise the slope to make better use of the rail-to-rail voltage range. For illustrative purposes, both channels in Figure 34 provide a 0.5 V/decade overall slope (25 mV/dB). Thus, using IREF = 3 μA, VLOG runs from 0.2 V at IPD = 3 nA to 1.4 V at IPD = 3 mA; the buffer output runs from 0.5 V to 3.5 V, corresponding to a dynamic range of 120 dB (electrical, that is, 60 dB optical power).

Further information on adjusting the slope and intercept, using a negative supply, and additional operations can be found in the AD8305 data sheet.

Figure 35 shows the improvement in accuracy when using a 2-point calibration method. To perform this calibration, apply two known currents, I1 and I2, in the linear operating range between 10 nA and 1 mA. Measure the resulting output, V1 and V2, respectively, and calculate the slope m and the intercept b:

m = (V1 – V2)/[log10(I1) – log10(I2)] (7)

b = V1 – m × log10(I1) (8) The same calibration could be performed with two known optical powers, P1 and P2. This allows for calibration of the entire measurement system while providing a simplified relationship between the incident optical power and VLOG voltage:

m = (V1 – V2)/(P1 – P2) (9) b = V1 – m × P1

(10)

CALIBRATION

Each channel of the ADL5310 has a nominal slope and intercept at LOG1 (LOG2) of 200 mV/decade and 300 pA, respectively, when configured as shown in Figure 34. These values are untrimmed and the slope alone may vary by as much as 7.5% over temperature. For this reason, it is recommended that a simple calibration be done to achieve increased accuracy. While the ADL5310 offers improved slope and intercept matching compared to a randomly selected pair of AD8305 log amps, the specified accuracy can only be achieved by calibrating each channel individually.

1.41.21.00.80.60.40.201nIDEAL OUTPUTCALIBRATED ERRORMEASURED OUTPUTUNCALIBRATED ERROR43210–1–2–310m04415-0-035The uncalibrated error line in Figure 35 was generated assum-ing that the slope of the measured output was 200 mV/decade when in fact it was actually 194 mV/decade. Correcting for this discrepancy decreased measurement error up to 3 dB.

MINIMIZING CROSSTALK

Combining two high-dynamic-range logarithmic converters in one IC carries potential pitfalls concerning channel-to-channel isolation. Special care must be taken in several areas to ensure acceptable crosstalk performance, particularly when one or both channels may operate at very low input currents. Fastidious sup-ply bypassing—also necessary for overall stability—and careful board layout are important first steps for minimizing crosstalk. While the shared bias circuitry improves channel-to-channel matching and reduces power consumption, it is also a source of crosstalk that must be mitigated. The VSUM pins, which are internally shorted, should be bypassed with at least 1 nF to ground, and 20 nF is recommended for operation at the lowest currents (<30 nA). VSUM is of particular importance because it acts as a reference voltage input for each input system, but without the bandwidth limitation at low currents that the primary inputs incur. Disturbances at the VSUM pin that are well within the bandwidth of the input are tracked by the loop and do not generate disturbances at the output (aside from the generally minor perturbation in reference currents caused by voltage variations at IRF1 and IRF2).

For this reason, the pole frequency at VSUM, which has a 16 kΩ typical source resistance, should be set below the minimum input system bandwidth for the lowest input current to be encountered. Because the low frequency noise at VSUM is also tracked by the loop within its available bandwidth, this is also a criterion for reducing the noise contribution at the output from the thermal noise of the 16 kΩ source resistance at VSUM.

10n100n1µ10µ100µ1mIPD (A)ERROR (dB (10mV/dB))VLOG(V)

Figure 35. Using 2-Point Calibration to Increase Measurement Accuracy

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ADL5310relative gain or absorbance measurement. A more straight-forward analog implementation includes the use of a current mirror, as shown in Figure 37. The current mirror is used to feed an opposite polarity replica of the cathode photocurrent of PD2 into Channel 2 of the ADL5310. This allows one channel to be used as an absolute power meter for the optical signal

incident on PD2, while the opposite channel is used to directly compute the log ratio of the two input signals.

5V0.1µFVSUM1nF5VVPOSOUT2Φ2*A 10 nF capacitor on each VSUM pin (20 nF parallel equivalent) combined with the 16 kΩ source resistance yields a 500 Hz pole, which is sufficiently below the bandwidth for the minimum input current of 3 nA.

Residual crosstalk disturbance is particularly problematic at the lowest currents for two reasons. First, the loop is unable to reject summing node disturbances beyond the limited bandwidth. Second, the settling response at the lowest currents to any residual disturbance is significantly slower than that for input currents even one or two decades higher (see Figure 18).

12ACTIVE CHANNEL OUTPUT PULSE, 1-DECADE STEP3µA TO 30µA1.2ADL5310COMMINACTIVE CHANNEL OUTPUT (mV)91.0ACTIVE CHANNEL OUTPUT (V)IIN2=IPD21kΩ4.7nFINP2IIN2*Φ2(V)≅0.2log10100pA()SCL2BIN2log6IINP– 3nA3IINP– 10nAIINP– 100nA0.8ITEMPERATURELOG2COMPENSATIONLOG21nF0.60IINP– 30nA–3INACTIVE CHANNEL RESPONSE0.42MΩ1kΩ4.7nFIRF2VRDZVREFlogOUT1BIASGENERATORIIN1**α21(V)≅0.2log10IPD2α21**0.200.51.01.52.004415-0-036–6TIME (ms)02.5()SCL1BIN1IPD2IRF1

logFigure 36. Crosstalk Pulse Response for Various Input Current Values

PD2InGaAs PIN1kΩ4.7nFITEMPERATURELOG1COMPENSATIONLOG11nFFigure 36 shows the measured response of an inactive channel (dc input) to a 1-decade current step on the input of the active channel for several inactive channel dc current values. Addi-tional system considerations may be necessary to ensure

adequate settling time following a known transient when one or both channels are operating at very low input currents.

5VPD1InGaAs PINIIN11kΩ0.1µFINP1logCOMM04415-0-0374.7nFVSUM1nFVNEGCOMM

RELATIVE AND ABSOLUTE POWER MEASUREMENTS

When properly calibrated, the ADL5310 provides two inde-pendent channels capable of accurate absolute optical power measurements. Often, it is desirable to measure the relative gain or absorbance across an optical network element, such as an optical amplifier or variable attenuator. If each channel has identical logarithmic slopes and intercepts, this can easily be done by differencing the output signals of each channel. In reality, channel mismatch can result in significant errors over a wide range of input levels if left uncompensated. Postprocessing of the signal can be used to account for individual channel characteristics. This requires a simple calculation of the expected input level for a measured log voltage, followed by differencing of the two signal levels in the digital domain for a

Figure 37. Absolute and Relative Power Measurement Application

Using Modified Wilson Current Mirror

The presented current mirror is a modified Wilson mirror.

Other current mirror implementations would also work, though the modified Wilson mirror provides fairly constant perfor-mance over temperature. It is essential to use matched pair transistors when designing the current mirror to minimize the effects of temperature gradients and beta mismatch.

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ADL5310

The solution in Figure 37 is no longer subject to potential

channel mismatch issues. Individual channel slope and intercept characteristics can be calibrated independently. The accuracy was verified using a pair of calibrated current sources. The performance of the circuit depicted in Figure 37 is shown in Figure 38 and Figure 39. Multiple transfer functions and error plots are provided for various power levels. The accuracy is better than 0.1 dB over a 5-decade range. The dynamic range is slightly reduced for strong IIN input currents. This is due to the limited available swing of the VLOG pin and can be recovered through careful selection of input and output optical tap coupling ratios.

1.81.61.4OUTPUT VOLTAGE (V)CHARACTERIZATION METHODS

During the characterization of the ADL5310, the device was treated as a precision current-input logarithmic converter, because it is impractical to generate accurate photocurrents by illuminating a photodiode. The test currents were generated by using either a well-calibrated current source, such as the

Keithley 236, or a high value resistor from a voltage source to the input pin. Great care is needed when using very small input currents. For example, the triax output connection from the current generator was used with the guard tied to VSUM. The input trace on the PC board was guarded by connecting adjacent traces to VSUM.

These measures are needed to minimize the risk of leakage current paths. With 0.5 V as the nominal bias on the INP1

(INP2) pin, a leakage-path resistance of 1 GΩ to ground would subtract 0.5 nA from the input, which amounts to a −1.6 dB error for a 3 nA source current. Additionally, the very high sensitivity at the input pins and the long cables commonly needed during characterization allow 60 Hz and RF emissions to introduce substantial measurement errors. Careful guarding techniques are essential to reducing the pickup of these spurious signals.

φ2 WHENIPD1 = 100µA1.21.00.80.60.40.204415-0-038α21 FOR MULTIPLE VALUES OF IPD10–20–100102030405060Additional information, including test setups, can be found in the AD8305 and ADL5306 data sheets.

LOG10 [IPD1/IPD2] (dB)

Figure 38. Absorbance and Absolute Power Transfer Functions for

Wilson Mirror ADL5310 Combination

0.50.40.30.2ERROR (dB)IPD1=1µA0.10–0.1IPD1=10µA–0.2–0.3–0.4–0.5–40–30–20–10IPD1= 100µA04415-0-0390102030405060LOG10 [IPD1/IPD2] (dB)

Figure 39. Log Conformance for Wilson Mirror ADL5310 Combination,

Normalized to 10 mA Channel 1 Input Current, IIN1

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ADL5310EVALUATION BOARD

An evaluation board is available for the ADL5310 (Figure 40 shows the schematic). It can be configured for a wide variety of experiments. The gain of each buffer amp is factory-set to unity, providing a slope of 200 mV/dec, and the intercept is set to 300 pA. Table 4 describes the various configuration options.

Table 4. Evaluation Board Configuration Options

Component Function P1 Supply Interface. Provides access to the Supply Pins VNEG, COMM, and

VPOS.

P2, R1, R3, R8, R9, Monitor Interface. By adding 0 Ω resistors to R1, R3, R8, R9, R17, R22, and R17, R22, R25, R30 R25, the VRDZ, VREF, VSUM, BIN1, BIN2, OUT1, and OUT2 pin voltages

can be monitored using a high impedance probe. VBIAS allows for the external bias voltages to be applied to J1 and J2. If R30 = 0 Ω, VBIAS = VREF.

Buffer Amplifier/Output Interface. The logarithmic slopes of the ADL5310 R5, R6, R7, R16,

can be altered using each buffer’s gain-setting resistors, R5 and R6, and R18, R19, R20,

R21, R31, R32, C4, R18 and R19. R7, R16, R31, R32, C19, and C20 allow for variation in the

buffer loading. R20, R21, C4, C14, C15, and C16 are provided for a variety C14, C15, C16,

of filtering applications. C19, C20

Default Condition

P1 = installed

P2 = not installed

R1 = R3 = R8 = open (size 0402) R9 = R17 = open (size 0402)

R22 = R25 = R30 = open (size 0402) R5 = R19 = 0 Ω (size 0402) R7 = R16 = 0 Ω (size 0402) R20 = R21 = 0 Ω (size 0402) R6 = R18 = open (size 0402) R31 = R32 = open (size 0402) C4 = C14 = open (size 0402) C19 = C20 = open (size 0402) C15 = C16 = open (size 0402) LOG1 = OUT1 = installed LOG2 = OUT2 = installed

R28 = R29 = 665 kΩ (size 0402) R2 = 0 Ω (size 0402)

R2, R28, R29

R4, R10, R11, C2, C3, C5, C6, C8, C9 C1, C7

R12, R13, R14, R15, C10, C11, C12, C13 IREF, INPT

J1, J2

C2 = C5 = C9 = 100 pF (size 0402) C3 = C6 = C8 = 0.01 µF (size 0402) R4 = R10 = R11 = 0 Ω (size 0402)

Filtering VSUM. C1 = C7 = 0.01 µF (size 0402) Input Compensation. Provides essential HF compensation at the Input R12 = R15 = 1 kΩ (size 0402) Pins INP1, INP2, IRF1, and IRF2. R13 = R14 = 2 kΩ (size 0402)

C10 = C13 = 1 nF (size 0402) C11 = C12 = 4.7 nF (size 0402)

Input Interface. The test board is configured to accept current through the IREF = INPT = installed

SMA connectors labeled INP1 and INP2. Through-holes are provided to

connect photodiodes in place of the INP1 and INP2 SMAs for optical

interfacing. By removing R28 (R29 for INP2), a second current can be

applied to the IRF1 (IRF2 for INP2) input (also SMA) for evaluating the ADL5310 in log ratio applications.

SC-Style Photodiode. Provides for the direct mounting of SC-style J1 = J2 = open photodiodes.

Intercept Adjustment. The voltage dropped across Resistors R28 and R29 determines the intercept reference current for each log amp, nominally set to 3 µA using a 665 kΩ 1% resistor. R2 can be used to adjust the output offset voltage at the LOG1 and LOG2 outputs. Supply Decoupling.

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ADL5310

VRDZR3OPENVBIASR20ΩVNEGC3 0.01µFR40ΩC2100pFC1 0.01µFR28R29665kΩ665kΩR1OPEN123242322212019R7 0ΩR32OPENR8 OPENC4 OPENR5 0ΩC16OPENR6OPENC20OPENOUT13J2PHOTODIODE21OUT1VREFVNEGCOMMCOMMVRDZOUT1R200ΩR240ΩLOG1VSUMINP1VSUMINP1IRF1IRF2INP2VSUMSCL118BIN117LOG1R26 0ΩR27 0ΩR21C14OPENOPENR18C15OPEN0ΩR25OPENR22OPENR230ΩBIN1LOG2BIN2LOG2IRF1ADL5310LOG116LOG215BIN214SCL21345IRF26VNEGVNEGVPOSVPOSVREFINP2R151kΩC13R142kΩC12R132kΩC11R121kΩC101nFR9OPENOUT27101112R190ΩOUT112345678P204415-0-040VREFC5 100pFR100ΩC6 0.01µFC9 100pFR110ΩC8 0.01µF1nF4.7nF4.7nFR17OPENOUT2OUT2BIN1LOG1LOG2BIN2OUT2R16 0ΩR31OPENC19OPEN3J1PHOTODIODE21VBIASAGNDVPOS1P123VNEGC7 0.01µFVREFR30 OPENVBIAS

Figure 40. Evaluation Board Schematic

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140-0-51440Figure 41. Component-Side Layout

Rev. A | Page 19 of 20

ADL5310240-0-51440

Figure 42. Component-Side Silkscreen

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ADL5310

OUTLINE DIMENSIONS

4.00BSC SQ0.60 MAX0.60 MAX1918EXPOSEDPAD(BOTTOM VIEW)PIN 1INDICATOR241PIN1INDICATORTOPVIEW3.75BSC SQ0.50BSC0.500.400.302.252.10 SQ1.957613120.25 MIN2.50 REF1.000.850.8012° MAX0.80MAX0.65TYP0.05 MAX0.02 NOM0.20 REFCOPLANARITY0.08SEATINGPLANE0.300.230.18COMPLIANTTO JEDEC STANDARDS MO-220-VGGD-2

Figure 43. 24-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body

(CP-24-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range ADL5310ACP-R2 –40°C to +85°C ADL5310ACP-REEL7 –40°C to +85°C ADL5310-EVAL Package Description Package Outline 24-Lead LFCSP CP-24-1 24-Lead LFCSP CP-24-1 Evaluation Board Branding1

JQA JQA

Branding is as follows: Line 1 — JQA

Line 2 — Lot Code

Line 3 — (Date Code) Date Code is in YYWW format

1

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

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