FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20903-1E
FLASH MEMORYCMOS
M (4M × 16) BIT
MirrorFlashTM
MBM29PL65LM-90/10
sDESCRIPTION
MBM29PL65LM is of 67,108,8 bit capacity +3.0 V -only Flash memory enabling word write, both across- thechip, comprehensive erase and by-the-unit, individual sector erase.
Its CMOS peripheral circuitry contributes to significant saving in power consumption even at high-speed stand-by mode operation.
MBM29PL65LM consists of 4M x 16 bit Word mode and erases 128 sectors at ever 32K word. Its package typeis 48-pin TSOP.
Embedded Program AlgorithmTM, when executed with erase or program command sequences, automatically timesthe program pulse widths and verifies proper cell margin.
MBM29PL65LM, because of its capability in electrical data erase and program through write command, enablesto rewrite data within the internal system. It is a truly dependable device for vast application possibilities.
sPRODUCT LINE UP
Part No.
VCCVCCQ
Max Address Access Time Max CE Access Time Max Page Read Access Time
MBM29PL65LM-903.0 V to 3.6 V
VCC90 ns90 ns25 ns
MBM29PL65LM-103.0 V to 3.6 V
VCC100 ns100 ns30 ns
sPACKAGE
48-pin plastic TSOP (1) Marking Side (FPT-48P-M19) Notes: Programming in byte mode ( × 8) is prohibited.
Programming to the address that already contains data is prohibited. (It is mandatory to erase data prior to overprogram on the same address.
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MBM29PL65LM-90/10
sFEATURES
••••••••
MirrorFlash MemoryTM*1
0.23 µm Process Technology4 M × 16 bit configuration
Single 3.0 V read, program and erase
Standard 48-pin TSOP (1) (Package suffix : TN)Minimum 100,000 program/erase cyclesHigh performance Page mode (4 words)
Sector erase architecture (Sectors can be grouped in any given combination.)32K word sectors
Any combination of sectors can be concurrently erased. Also supports full chip erase.
HiddenROM RegionWrite Protect by WP pinEmbedded EraseTM*2 AlgorithmsEmbedded ProgramTM*2 Algorithms
Data Polling and Toggle Bit feature for detection of program or erase cycle completionAutomatic sleep modeErase Suspend/ResumeLowVCC write inhibitSector Group Protection
Extended Sector Group ProtectionFast Program
Temporary sector group unprotection
In accordance with CFI (Common Flash Memory Interface)•••••••••••••
*1 : MirrorFlashTM is a trademark of Fujitsu Limited.
*2 : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
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sPIN ASSIGNMENTTSOP(1)A15A14A13A12A11A10A9A8A21A20WERESETACCWPA19A18A17A7A6A5A4A3A2A11234567101112131415161718192021222324(Marking Side)4847454443424140393837363534333231302928272625A16VCCQVSSDQ15DQ7DQ14DQ6DQ13DQ5DQ12DQ4VCCDQ11DQ3DQ10DQ2DQ9DQ1DQ8DQ0OEVSSCEA0( FPT-48P-M19 )sPIN DESCRIPTIONS
Pin NameA21 to A0DQ15 to DQ0
CEOEWEWPACCRESETVCCVCCQVSS
Address InputsData Inputs/OutputsChip EnableOutput EnableWrite Enable
Hardware Write ProtectionHardware Program Acceleration
Hardware Reset Pin/Temporary Sector Group UnprotectionDevice Power SupplyOutput Power SupplyDevice Ground
Function
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sBLOCK DIAGRAMDQ15 to DQ0VCCVSSVCCQErase VoltageGeneratorInput/OutputBuffersWERESETWPACCStateControlCommandRegisterProgram VoltageGeneratorCEOEChip EnableOutput EnableLogicSTBData LatchSTBY-DecoderY-GatingTimer forProgram/EraseA21 to A2AddressLatchX-DecoderCell MatrixA1, A0sLOGIC SYMBOL22A21 to A0DQ 15 to DQ 0 CE OE WE WPACCRESET1
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MBM29PL65LM-90/10
sDEVICE BUS OPERATION
MBM29PL65LM User Bus Operations Table
Operation
Standby
Autoselect Manufacture Code*1Autoselect Device Code*1
CEOEWEA0HLL
XLLLHHHXXX
XHHHHLLXXX
XLHA0XA0LXXX
A1XLLA1XA1HXXX
A2XLLA2XA2LXXX
A3XLLA3XA3LXXX
A6XLLA6XA6LXXX
A9DQ15 to DQ0RESETWPXVIDVIDA9XA9XXXX
Hi-ZCodeCodeDOUTHi-Z*4*4*4Hi-ZX
HHHHHHVIDVIDLH
XXXXX*5HHXL
Read LOutputDisable
Write (Program/Erase) Enable Sector Group Protection*2Temporary Sector Group Unprotection Reset (Hardware)Sector Write Protection*3
LLLXXX
Legend : L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.Hi-Z = High-Z, VID = 11.5 V to 12.5 V
*1 : Manufacturer and device codes may also be accessed via a command register write sequence.
See “MBM29PL65LM Standard Command Definitions”.*2 : Refer to Sector Group Protection.*3 : Protects the first 32K words sector (SA0).
*4 : DIN or DOUT as required by command sequence, data pulling, or sector protect algorithm
*5 : If WP/ACC = VIL, the first sector remains protected.
If WP/ACC = VIH, the first sector will be protected or unprotected as determined by the method specified in “Sector Group Protection” in “s FUNCTIONAL DESCRIPTION”.
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MBM29PL65LM Standard Command Definitions Table*1
CommandSequence
Reset*2Reset*2AutoselectProgramChip EraseSector Erase
Program/Erase Suspend*3Program/Erase Resume*3Set to Fast Mode*4Fast Program*4
Reset from Fast Mode*5Write to Buffer
Program Buffer to Flash(Confirm)
Write to Buffer Abort Reset*6Extended Sector Group Protection*7,*8Query*9
HiddenROM Entry*10
HiddenROM Program *10,*11HiddenROM Exit*11
RAPA
BusWriteCyclesReq'd
First BusSecond BusThird BusWrite Write Write CycleCycleCycle
AddrDataAddrXXXh555h555h555h555h555h
F0h
—
Data—55h55h55h55h55h——55hPD
AddrData—555h555h555h555h555h——555h——SA—555hSGA—555h555h555h
—F0h90hA0h80h80h——20h——25h—F0h40h—88hA0h90h
Fourth Bus
Read/Write Cycle
Addr—RA*1300h*13PA555h555h—————SA——SGA*13
——PAXXXh
Data—RD*1304h*13PDAAhAAh—————0Fh——SD*13——PD00h
Fifth BusSixth BusWrite Write CycleCycle
AddrDataAddrData————
————
————
————
13346611322201341344
AAh2AAhAAh2AAhAAh2AAhAAh2AAhAAh2AAh
——
2AAh55h555h10h2AAh55h—————PA———————
—————PD———————
SA—————WBL———————
30h—————PD———————
XXXhB0hXXXh555h
30h
AAh2AAh
PA
XXXhA0hXXXh555hSA555hXXXh55h555h555h555h
90hXXXh00h*12AAh2AAh29h
—
55h—55h60h—55h55h55h
AAh2AAh60h98h
SGA—
AAh2AAhAAh2AAhAAh2AAh
= Address of the memory location to be read.
= Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16 and A15
will uniquely select any sector. See “Sector Address Table”
SGA = Sector Group Address to be protected. See “Sector Group Address Table”. Specify SGA which
constitutes from A21 to A17 and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0).
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.WBL = Write Buffer Location
HRA = Address of the HiddenROM area ; 000000h to 00007Fh
*1 : The command combinations not described in “MBM29PL65LM Standard Command Definitions” are
illegal.*2 : Both of these reset commands are equivalent except for \"Write to Buffer Abort\" reset.
*3 : The Erase Suspend and Erase Resume command are valid only during a sector erase operation.*4 : The Set to Fast Mode command is required prior to the Fast Program command.
*5 : The Reset from Fast Mode command is required to return to the read mode when the device is in fast
mode.6
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*6 : Reset to the read mode. The Write to Buffer Abort Reset command is required after the Write to Buffer
operation was aborted.*7 : This command is valid while RESET = VID.
*8 : Sector Group Address (SGA) with A6 = 0, A3 = 0, A2 = 0, A1 = 1, and A0 = 0*9 : The valid address are A6 to A0.
*10 : The HiddenROM Entry command is required prior to the HiddenROM programming.*11 : This command is valid during HiddenROM mode.*12 : The data “F0h” is also acceptable.*13 : Indicates read cycle.
Notes : • X = “H” or “L”
• Bus operations are defined in “User Bus Operations Table”.
Autoselect Codes Table
Type
Manufacturer’s CodeDevice Code
Extended Device Code*
1
A21 to A17
XXXX
Sector Group Address
A6VILVILVILVILVIL
A3VILVILVIHVIHVIL
A2VILVILVIHVIHVIL
A1VILVILVIHVIHVIH
A0VILVIHVILVIHVIL
Code (HEX)
04h227Eh2213h2201h*2
Sector Group Protection*3
*1 : At Word mode, a read cycle at address 01h outputs device code. When 227Eh is output, it indicates that reading
two additional codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these Extended Device Codes at the address of 0Eh, as well as at 0Fh.*2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.*3 : Given CE = Fix, wait for one cycle after the rising edge of WE (the last write command), then indicate SGA as (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0).
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Sector Address Table
SectorSA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10SA11SA12SA13SA14SA15SA16SA17SA18SA19SA20SA21SA22SA23SA24SA25SA26SA27SA28SA29SA30
A210000000000000000000000000000000
A200000000000000000000000000000000
A190000000000000000111111111111111
A180000000011111111000000001111111
A170000111100001111000011110000111
A160011001100110011001100110011001
A150101010101010101010101010101010
Sector Size (Kwords)
32323232323232323232323232323232323232323232323232323232323232
Address Range000000h to 007FFFh008000h to 00FFFFh010000h to 017FFFh018000h to 01FFFFh020000h to 027FFFh028000h to 02FFFFh030000h to 037FFFh038000h to 03FFFFh040000h to 047FFFh048000h to 04FFFFh050000h to 057FFFh058000h to 05FFFFh060000h to 067FFFh068000h to 06FFFFh070000h to 077FFFh078000h to 07FFFFh080000h to 087FFFh088000h to 08FFFFh090000h to 097FFFh098000h to 09FFFFh0A0000h to 0A7FFFh0A8000h to 0AFFFFh0B0000h to 0B7FFFh0B8000h to 0BFFFFh0C0000h to 0C7FFFh0C8000h to 0CFFFFh0D0000h to 0D7FFFh0D8000h to 0DFFFFh0E0000h to 0E7FFFh0E8000h to 0EFFFFh0F0000h to 0F7FFFh
(Continued)8
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Address Range
MBM29PL65LM
SectorSA31SA32SA33SA34SA35SA36SA37SA38SA39SA40SA41SA42SA43SA44SA45SA46SA47SA48SA49SA50SA51SA52SA53SA54SA55SA56SA57SA58SA59SA60SA61SA62
A2100000000000000000000000000000000
A2001111111111111111111111111111111
A1910000000000000000111111111111111
A1810000000011111111000000001111111
A1710000111100001111000011110000111
A1610011001100110011001100110011001
A1510101010101010101010101010101010
Sector Size
(Kwords)
3232323232323232323232323232323232323232323232323232323232323232
0F8000hto0FFFFFh100000h to 107FFFh108000h to 10FFFFh110000h to 117FFFh118000h to 11FFFFh120000h to 127FFFh128000h to 12FFFFh130000h to 137FFFh138000h to 13FFFFh140000h to 147FFFh148000h to 14FFFFh150000h to 157FFFh158000h to 15FFFFh 160000h to 167FFFh168000h to 16FFFFh170000h to 177FFFh178000h to 17FFFFh180000h to 187FFFh188000h to 18FFFFh190000h to 197FFFh198000h to 19FFFFh1A0000hto1A7FFFh1A8000hto1AFFFFh1B0000hto1B7FFFh1B8000hto1BFFFFh1C0000hto1C7FFFh1C8000hto1CFFFFh1D0000hto1D7FFFh1D8000hto1DFFFFh1E0000hto1E7FFFh1E8000hto1EFFFFh1F0000hto1F7FFFh
(Continued)9
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SectorSA63SASA65SA66SA67SA68SA69SA70SA71SA72SA73SA74SA75SA76SA77SA78SA79SA80SA81SA82SA83SA84SA85SA86SA87SA88SASA90SA91SA92SA93SA94
A2101111111111111111111111111111111
A2010000000000000000000000000000000
A1910000000000000000111111111111111
A1810000000011111111000000001111111
A1710000111100001111000011110000111
A1610011001100110011001100110011001
A1510101010101010101010101010101010
Sector Size (Kwords)
3232323232323232323232323232323232323232323232323232323232323232
Address Range1F8000h to 1FFFFFh200000h to 207FFFh208000h to 20FFFFh210000h to 217FFFh218000h to 21FFFFh220000h to 227FFFh228000h to 22FFFFh230000h to 237FFFh238000h to 23FFFFh240000h to 247FFFh248000h to 24FFFFh250000h to 257FFFh258000h to 25FFFFh260000h to 267FFFh268000h to 26FFFFh270000h to 277FFFh278000h to 27FFFFh280000h to 287FFFh288000h to 28FFFFh290000h to 297FFFh298000h to 29FFFFh2A0000h to 2A7FFFh2A8000h to 2AFFFFh2B0000h to 2B7FFFh2B8000h to 2BFFFFh2C0000h to 2C7FFFh2C8000h to 2CFFFFh2D0000h to 2D7FFFh2D8000h to 2DFFFFh2E0000h to 2EE7FFh2E8000h to 2EFFFFh2F0000h to 2F7FFFh
(Continued)10
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Address Range
MBM29PL65LM
(Continued)SectorSA95SA96SA97SA98SA99SA100SA101SA102SA103SA104SA105SA106SA107SA108SA109SA110SA111SA112SA113SA114SA115SA116SA117SA118SA119SA120SA121SA122SA123SA124SA125SA126SA127
A21111111111111111111111111111111111
A20011111111111111111111111111111111
A19100000000000000001111111111111111
A18100000000111111110000000011111111
A17100001111000011110000111100001111
A16100110011001100110011001100110011
A15101010101010101010101010101010101
Sector Size
(Kwords)
323232323232323232323232323232323232323232323232323232323232323232
2F8000hto2FFFFFh300000h to 307FFFh308000h to 30FFFFh310000h to 317FFFh318000h to 31FFFFh320000h to 327FFFh328000h to 32FFFFh330000h to 337FFFh338000h to 33FFFFh340000h to 347FFFh348000h to 34FFFFh350000h to 357FFFh358000h to 35FFFFh 360000h to 367FFFh368000h to 36FFFFh370000h to 377FFFh378000h to 37FFFFh380000h to 387FFFh388000h to 38FFFFh390000h to 397FFFh398000h to 39FFFFh3A0000hto3A7FFFh3A8000hto3AFFFFh3B0000hto3B7FFFh3B8000hto3BFFFFh3C0000hto3C7FFFh3C8000hto3CFFFFh3D0000hto3D7FFFh3D8000hto3DFFFFh3E0000hto3E7FFFh3E8000hto3EFFFFh3F0000hto3F7FFFh3F8000hto3FFFFFh
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Sector Group Address Table
Sector GroupAddress
SGA0SGA1SGA2SGA3SGA4SGA5SGA6SGA7SGA8SGA9SGA10SGA11SGA12SGA13SGA14SGA15SGA16SGA17SGA18SGA19SGA20SGA21SGA22SGA23SGA24SGA25SGA26SGA27SGA28SGA29SGA30SGA31
A2100000000000000001111111111111111
A2000000000111111110000000011111111
A1900001111000011110000111100001111
A1800110011001100110011001100110011
A1701010101010101010101010101010101
Sector Group Size
(Kwords)
128128128128128128128128128128128128128128128128128128128128128128128128128128128128128128128128
Sectors SA0toSA3 SA4toSA7 SA8toSA11 SA12toSA15 SA16toSA19 SA20toSA23 SA24toSA27 SA28toSA31 SA32toSA35 SA36toSA39 SA40toSA43 SA44toSA47 SA48toSA51 SA52toSA55SA56toSA59SA60toSA63SAtoSA67SA68toSA71SA72toSA75SA76toSA79SA80toSA83SA84toSA87SA88toSA91SA92toSA95SA96toSA99SA100 to SA103SA104 to SA107SA108 to SA111SA112 to SA115SA116 to SA119SA120 to SA123SA124 to SA127
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Common Flash Memory Interface Code Table
DQ15 to DQ0Description0051h0052hQuery-unique ASCII string “QRY”0059h0002hPrimary OEM Command Set0000h02h : AMD/FJ standard0040h
Address for Primary Extended Table
0000h0000hAlternate OEM Command Set0000h(00h = not applicable)0000h
Address for Alternate OEM Extended Table
0000h
VCC Min (write/erase)
0027hDQ7 to DQ4: 1V/bit,
DQ3 to DQ0: 100 mV/bitVCC Max (write/erase)
0036hDQ7 to DQ4: 1V/bit,
DQ3 to DQ0: 100 mV/bit
0000hVPP Min voltage (00h = no Vpp pin)0000hVPP Max voltage (00h =no Vpp pin)0007hTypical timeout per single write 2N µs0007hTypical timeout for Min size buffer write 2N µs000AhTypical timeout per individual sector erase 2N ms0000hTypical timeout for full chip erase 2N ms0001hMax timeout for write 2N times typical0005hMax timeout for buffer write 2N times typical0004hMax timeout per individual sector erase 2N times typical0000hMax timeout for full chip erase 2N times typical0017hDevice Size = 2N byte0001hFlash Device Interface description0000h01h : × 160005h
Max number of byte in multi-byte write = 2N
0000h0001hNumber of Erase Block Regions within device (02h = Boot)007FhErase Block Region 1 Information0000hbit 15 to bit 0 : y = number of sectors0000hbit 31 to bit 16 : z = size0001h (z × 256 Byte) 0000hErase Block Region 2 Information0000hbit 15 to bit 0 : y = number of sectors0000hbit 31 to bit 16 : z = size0000h (z × 256 Byte)
A6 to A0
10h11h12h13h14h15h16h17h18h19h1Ah1Bh
1Ch1Dh1Eh1Fh20h21h22h23h24h25h26h27h28h29h2Ah2Bh2Ch2Dh2Eh2Fh30h31h32h33h34h
(Continued)13
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(Continued)A6 to A0
35h36h37h38h39h3Ah3Bh3Ch40h41h42h43h44h
45h46h47h
DQ15 to DQ0
0000h0000h0000h0000h0000h0000h0000h0000h0050h0052h0049h0031h0033h0008h0002h0004h
Description
Erase Block Region 3 Information
bit 15 to bit 0 : y = number of sectorsbit 31 to bit 16 : z = size (z × 256 Byte)
Erase Block Region 4 Information
bit 15 to bit 0 : y = number of sectorsbit 31 to bit 16 : z = size (z × 256 Byte)
Query-unique ASCII string “PRI”
Major version number, ASCIIMinor version number, ASCIIAddress Sensitive Unlock08h : Supported09h : Not SupportedErase Suspend
(02h = To Read & Write)Sector Group Protection00h : Not Supported
X : Number of sectors in per groupSector Temporary Unprotection00h : Not Supported01h : Supported
Sector Group Protection AlgorithmDual Operation
(00h = Not Supported)Burst Mode Type
(00h = Not Supported)Page Mode Type
(01h = 4-Word Page Supported)VACC (Acceleration) Supply Minimum00h = Not SupportedDQ7 to DQ4: 1V/bit, DQ3 to DQ0: 100mV/bit
VACC (Acceleration) Supply Maximum00h = Not SupportedDQ7 to DQ4: 1V/bit, DQ3 to DQ0: 100mV/bitWrite Protect
04h = Uniform Sectors Bottom Write ProtectProgram Suspend00h = Not Supported01h = Supported
48h49h4Ah4Bh4Ch
0001h0004h0000h0000h0001h
4Dh00B5h
4Eh00C5h
4Fh50h
0004h01h
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MBM29PL65LM-90/10
sFUNCTIONAL DESCRIPTION
Standby Mode
There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, andthe other via the RESET pin only.When using both pins, CMOS standby mode is achieved with CE and RESET input held at VCC ± 0.3 V. Underthis condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC activecurrent (ICC2) is required even when CE = “H”. The device can be read with standard access time (tCE) from eitherof these standby modes.
When using the RESET pin only, CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE =“H” or “L”) .
Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is set high, the devicerequires tRH as a wake-up time for output to be valid for read access.
During standby mode, the output is in the high impedance state regardless of OE input.Automatic Sleep Mode
Automatic sleep mode works to resin power consumption during read-out of the device data. This is useful inthe application such as a handy terminal which requires low power consumption.
To activate this mode, the device automatically switches itself to low power mode when address remain stableduring
access time of tACC + 30 ns. It is not necessary to control CE, WE and OE on this mode. The current consumedis typically 1 µA (CMOS Level) .
During simultaneous operation, VCC active current (ICC2) is required.
Since, the data are latched during this mode, the data are continuously read out. When the addresses arechanged, the mode is automatically canceled and the device reads the data for changed address.Autoselect
Autoselect mode allows reading out of a binary code and identifies its manufacturer and type. It is intended foruse by programming equipment for the purpose of automatically matching the device to be programmed withits corresponding programming algorithm. This mode is functional over the entire temperature range of the device.To activate this mode, the programming equipment must force VID on address pin A9. Three identifier bytes maythen be sequenced from the device outputs by toggling addresses. All addresses are DON’T CARES except A6to A0.
The manufacturer and device codes may also be read via the command register, for instances when the deviceis erased or programmed in a system without access to high voltage on the A9 pin. The command sequence isillustrated in “Common Definitions Table” of “s DEVICE BUS OPERATIONS”.
A read cycle from address 00h returns the manufacturer’s code (Fujitsu = 04h) . A read cycle from address 01houtputs device code. At word mode, 227Eh is output, it indicates that two additional codes, called ExtendedDevice Codes is required. Therefore the system may continue reading out these Extended Device Codes ataddresses of 0Eh and 0Fh. Refer to “Autoselect Codes Table” in “s DEVICE BUS OPERATIONS”.Read Mode
The device has two control functions required to obtain data at the outputs. CE is the power control and usedfor a device selection. OE is the output control and used to gate data to the output pins if a device is selected.Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enableaccess time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The outputenable access time is the delay from the falling edge of OE to valid data at the output pins. Assuming theaddresses have been stable for at least tACC - tOE time. When reading out a data without changing addressesafter power-up, input hardware reset or to change CE pin from “H” or “L”.15
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Page Mode Read
The device is capable of fast Page mode read and are compatible with Page mode Mask ROM read operation.This mode provides faster read access speed for random locations within a page. Page size is 4 words, withinthe appropriate Page being selected by the higher address bits A21 to A2 and the address bits A1 to A0 in Wordmode (A1 to A-1 in Byte mode). The initial page access is equal to the random access (tACC) and subsequentPage read access (as long as the locations specified by the microprocessor fall within that Page) is equivalentto the page access time (tPACC).Output Disable
With the OE input is at logic high level (VIH), output from the device is disabled. This causes the output pins tobe in a high impedance state.Write
Device erase and programming are accomplished via the command register. The contents of the register serveas input to the internal state machine. The state machine output dictates the device function.
The command register itself does not occupy any addressable memory location. The register is a latch used tostore the commands, along with the address and data information needed to execute the command. The com-mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on thefalling edge of WE or CE, whichever starts later, while data is latched on the rising edge of WE or CE, whicheverstarts first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.Sector Group Protection
The device features hardware sector group protection. This feature will disable both program and erase opera-tions in any combination of 32 sector groups of memory. See “Sector Group Address Table (MBM29PL65LM)”in “s DEVICE BUS OPERATION”. The user’s side can use the sector group protection using programmingequipment. The device is shipped with all sector groups that are unprotected.
To activate it, the programming equipment must force VID on address pin A9 and control pin OE, CE = VIL andA6 = A3 = A2 = A0 = VIL, A1 = VIH. The sector group addresses (A21, A20, A19, A18, and A17) should be set to thesector to be protected. “Sector Address Table (MBM29PL65LM)” in “s DEVICE BUS OPERATION” defines thesector address for each of the seventy-one (71) individual sectors, and “Sector Group Address Table(MBM29PL65LM)” in “s DEVICE BUS OPERATION” defines the sector group address for each of the twenty-four (24) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WEpulse and is terminated with the rising edge of the same. Sector group addresses must be held constant duringthe WE pulse. See “Sector Group Protection Timing Diagram” in “s TIMING DIAGRAM” and “Sector GroupProtection Algorithm” in “s FLOW CHART” for sector group protection timing diagram and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A21, A20, A19, A18 and A17) while (A6,A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwisethe device will produce “0” for unprotected sectors. In this mode, the lower order addresses, except for A0, A1,A2, A3 and A6 can be either High or Low.
Where the high order addresses (A21, A20, A19, A18 and A17) are the desired sector group address will produce alogical “1” at DQ0 for a protected sector group. See “Sector Group Protection Verify Autoselect Codes” in “s DEVICE BUS OPERATION” for Autoselect codes.Temporary Sector Group Unprotection
This feature allows temporary unprotection of previously protected sector groups of the devices in order to changedata. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID). Duringthis mode, formerly protected sector groups can be programmed or erased by selecting the sector group ad-dresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be16
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protected again. Refer to “Temporary Sector Group Unprotection Timing Diagram” in s SWITCHING WAVE-FORMS and “Temporary Sector Group Unprotection Algorithm” in s FLOW CHART.Hardware Reset
The device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has tobe kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the processof being executed is terminated and the internal state machine is reset to the read mode “tREADY” after the RESETpin is driven low.
Furthermore once the RESET pin goes high the device requires an additional “tRH” before it allows read access. When the RESET pin is low, the device is in the standby mode for the duration of the pulse and all the dataoutput pins are tri-stated. If a hardware reset occurs during a program or erase operation, the data at thatparticular location are corrupted. Write Protect (WP)Aside from Sector Group Protection, MBM29PL65LM provides another function that protects the first sector(SA0) during programming and erase. When WP = VIL, this first sector (SA0) becomes protected while SectorGroup Protection for all the other sectors are temporarily lifted.Accelerated Program Operation
The device offers accelerated program operation which enables the programming in high speed. If the systemasserts VACC to the ACC pin, the device automatically enters the acceleration mode and the time required forprogram operation will reduce to about 85%. This function is primarily intended to allow high speed program,so caution is needed as the sector group becomes temporarily unprotected.
The system uses fast program command sequence when programming during acceleration mode. Set commandto fast mode and reset command from fast mode are not necessary. When the device enters the accelerationmode, the device automatically set to fast mode. Therefore the present sequence is used for programming anddetection of completion during acceleration mode.
Removing VACC from the ACC pin and applying VIL or VIH returns the device to normal operation. Do not removeVACC from ACC pin while programming. See “Accelerated Program Timing Diagram”.VCCQ
The output voltage generated on the device is determined based on the VCCQ level. This feature allows the deviceto operate in mixed-voltage environments, driving and receiving signals to and from other devices on the samebus.
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sCOMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register. \"MBM29PL65LM Command Definitions Table\" in s DEVICE BUS OPERATION shows the valid register com-mand sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only whilethe Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h) com-mands are valid only while the Program operation is in progress. Moreover, Read/Reset commands are func-tionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ7to DQ0 and DQ15 to DQ8 bits are ignored.Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Reset mode, verify mode ofsecter protect commands, the Read/Reset operation is initiated by writing the Read/Reset command sequenceinto the command register. Microprocessor read cycles retrieve array data from the memory. The device remainsenabled for reads until the command register contents are altered.
The device automatically powers-up in the Read/Reset state. In this case, a command sequence is not requiredto read data. Standard microprocessor read cycles retrieve array data. This default value ensures that no spuriousalteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics andWaveforms for specific timing parameters. Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. Thereforemanufacture and device codes must be accessible while the device resides in the target system. PROM pro-grammers typically access the signature codes by raising A9 to a higher voltage. However multiplexing highvoltage onto the address lines is not generally desired system design practice.
he device contains Autoselect command operation to supplement traditional PROM programming methodology.The operation is initiated by writing the Autoselect command sequence into the command register.
This is followed by a third write cycle that contains the address and the Autoselect command. Then the manu-facture and device codes can be read from the address, and an actual data of memory cell can be read fromthe another address.
Following the command write, a read cycle from address 00h returns the manufacturer’s code (Fujitsu=04h).And, at double word mode, a read cycle at address 01h outputs device code. At word mode, 227Eh is output,this indicates that two additional codes, called Extended Device Codes will be required. Therefore the systemmay continue reading out these Extended Device Codes at the address of 0Eh, as well as at (BA) 0Fh (at wordmode, 1Eh). Refer to \"MBM29PL65LX Autoselect Codes Table\" in s DEVICE BUS OPERATION.
To terminate the operation, it is necessary to write the Reset command sequence into the register. To executethe Autoselect command during the operation, Reset command sequence must be written before the Autoselectcommand.Program Command
The device is programmed on word-by-word basis (or double word-by-double word). Programming is a four buscycle operation. There are two “unlock” write cycles. These are followed by the program set-up command anddata write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later, and the datais latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whicheverhappens first) starts programming. Upon executing the Embedded Program Algorithm command sequence, thesystem is not required to provide further controls or timings. The device automatically provides adequate inter-nally generated program pulses and verify programmed cell margin.
The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit) orRY/BY. The Data Polling and Toggle Bit are automatically performed at the memory location being programmed.
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The programming operation is completed when the data on DQ7 is equivalent to data written to this bit at whichthe devices return to the read mode and plogram addresses are no longer latched. Therefore, the devices requirethat a valid address to the devices be supplied by the system at this particular instance. Hence Data Pollingrequires the same address which is being programmed.
If hardware reset occurs during the programming operation, the data being written is not guaranteed.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot beprogrammed back to a “1”. Attempting to do so may either hang up the device or result in an apparent successaccording to the data polling algorithm but a read from Reset mode will show that the data is still “0”. Only eraseoperations can convert from “0”s to “1”s.Refer to \"Embedded ProgramTM Algorithm\" using typical commandstrings and bus operations.
Program Suspend/Resume Command
The Program Suspend command allows the system to interrupt a program operation so that data can be readfrom any address. Writing the Program Suspend command (B0h) during the Embedded Program operationimmediately suspends the programming. The bank addresses of sector being programmed should be set whenwriting the Program Suspend command.
When the Program Suspend command is written during a programming process, the device halts the programoperation within 1 µs and updates the status bits.
After the program operation has been suspended, the system can read data from any address. The data atprogram-suspended address is not valid. Normal read timing and command definitions apply.
After the Program Resume command (30h) is written, the device reverts to programming. The bank addressesof sectors being suspended should be set when writing the Program Resume command. The system candetermine the program operation status using the DQ7 or DQ6 status bits, just as in the standard programoperation. See “Write Operation Status” for more information. When issuing program suspend command in4 µs after issuing program command, determine the status of program operation by reading status bit at more4 µs after issuing program resume command.
The system may also write the Autoselect command sequence in the Program Suspend mode.
The device allows reading Autoselect codes at the addresses within programming sectors, since the codes arenot stored in the memory. When the device exits from the Autoselect mode, the device reverts to the ProgramSuspend mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more infor-mation.
The system must write the Program Resume command to exit from the Program Suspend mode and continueprogramming operation. Further writes of the Resume command are ignored. Another Program Suspend com-mand can be written after the device resumes programming.
Do not read CFI code after HiddenROM Entry and Exit in program suspend mode.Write Buffer Programming Operations
Write Buffer Programming allows the system write to series of 16 words in one programming operation. Thisresults in faster effective word programming time than the standard programming algorithms. The Write BufferProgramming command sequence is initiated by first writing two unlock cycles. This is followed by a third writecycle selecting the Sector Address in which programming will occur. In forth cycle contains both Sector Addressand unique code for data bus width will be loaded into the page buffer at the Sector Address in which programmingwill occur.
The system then writes the starting address/data combination. This “starting address” must be the same SectorAddress used in third and fourth cycles and its lower addresses of A3 to A0 should be 0h. All subsequent addressmust be incremented by 1. Addresses are latched on the falling edge of CE or WE, whichever happens laterand the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE(whichever happens first) starts programming. Upon executing the Write Buffer Programming Operations com-
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mand sequence, the system is not required to provide further controls or timings. The device will automaticallyprovide adequate internally generated program pulses and verify the programmed cell margin.
DQ7(Data Polling), DQ6(Toggle Bit), DQ5(Exceeded Timing Limits), DQ1(Write-to-Buffer Abort) should be moni-tored to determine the device status during Write Buffer Programming. In addition to these functions, it is alsopossible to indicate to the host system that Write Buffer Programming Operations are either in progress or havebeen completed by RY/BY. See “Hardware Sequence Flags”.The Data polling techniques described in “DataPolling Algorithm” in s FLOW CHART should be used while monitoring the last address location loaded into thewrite buffer. In addition, it is not neccessary to specify an address in Toggle Bit techniques described in “ToggleBit Algorithm” in s FLOW CHART. The automatic programing operation is completed when the data on DQ7 isequivalent to the data written to this bit at which time the device returns to the read mode and addresses areno longer latched ( See \"Hardware Sequence Flags\").
The write-buffer programming operation can be suspended using the standard program suspend/resume com-mands.
Once the write buffer programming is set, the system must then write the “Program Buffer to Flash” commandat the Sector Address. Any other address/data combination will abort the Write Buffer Programming operationand the device will continue busy state.
The Write Buffer Programming Sequence can be ABORTED by doing the following :
• Different Sector Address is asserted.
• Write data other than the “Program Buffer to Flash\" command after the specified number of “data load” cycles.A “Write-to-Buffer-Abort Reset” command sequence must be written to the device to return to read mode. (See“MBM29PL65LM Standard Command Definitions” in s DEVICE BUS OPERATION for details on this commandsequence.)
Chip Erase Command
Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program prior to erase. Upon executing the Embedded Erase Algorithmcommand sequence the device automatically programs and verifies the entire memory for an all zero data patternprior to electrical erase. (Preprogram Function) The system is not required to provide any controls or timingsduring these operations.
The system can determine the erase operation status by using DQ7 (Data Polling), or DQ6 (Toggle Bit). The chiperase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence andterminates when the data on DQ7 is “1” at which the device returns to read the mode.Chip Erase Time: Sector Erase Time × All sectors + Chip Program Time (Preprogramming)Refer to \"Embedded EraseTM Algorithm\" for typical command strings and bus operations.Sector Erase Command
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sectoraddress (any address location within the desired sector) is latched on the falling edge of CE or WE whicheverstarts later, while the command (Data = 30h) is latched on the rising edge of CE or WE whichever states first.After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation will begin.Multiple sectors are erased concurrently by writing the six bus cycle operations on \"MBM29XL12DF CommandDefinitions Table\" in s DEVICE BUS OPERATION. This sequence is followed with writes of the Sector Erasecommand to addresses in other sectors desired to be concurrently erased. The time between writes must beless than “tTOW” otherwise that command is not accepted and erasure does not start. It is recommended thatprocessor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabledafter the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of last CE or WE whicheverstarts first initiates the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever20
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starts first occurs within the “tTOW” time-out window the timer is reset. (Monitor DQ3 to determine if the sectorerase timer window is still open, see section DQ3, \"Sector Erase Timer\".) Any command other than Sector Eraseor Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previouscommand string. Resetting the device once execution has begun may corrupt the data in the sector. In that caserestart the erase on those sectors and allow them to complete. Refer to \"Write Operation Status\" section forSector Erase Timer operation. Loading the sector erase buffer may be done in any sequence and with anynumber of sectors.
Sector erase does not require the user to program prior to erase. The device automatically programs all memorylocations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing a sector orsectors the remaining unselected sectors are not affected. The system is not required to provide any controlsor timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling), or DQ6 (Toggle Bit). The sector erase begins after the “tTOW” time out from the rising edge of CE or WE whichever starts first for thelast sector erase command pulse and terminates when the data on DQ7 is “1” at which time the device returnsto the read mode. See \"Write Operation Status\" section. Data polling and Toggle Bit must be performed at anaddress within any of the sectors being erased.
Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] × Number of SectorErase.
Erase Suspend/Resume Command
The Erase Suspend command allows the user to interrupt Sector Erase operation and then perform read to asector not being erased. This command is applicable ONLY during the Sector Erase operation within the time-out period for Sectore erase.
Writting the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate terminationof the time-out period and suspension of the erase operation.
Writing the Erase Resume command (30h) resumes the erase operation.
When the “Erase Suspend” command is written during the Sector Erase operation, the device takes a maximumof “tSPD” to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/BY output pin will be at High-Z and the DQ7 bit will be at logic “1” and DQ6 will stop toggling. The user must usethe address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been sus-pended. Further writes of the Erase Suspend command are ignored.
When the erase operation is suspended, the device defaults to the erase-suspend-read mode. Reading data inthis mode is the same as reading from the standard read mode except that the data must be read from sectorsthat have not been erase-suspended. Successively reading from the erase-suspended sector while the deviceis in the erase-suspend-read mode causes DQ2 to toggle. See the section on DQ2.
To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes ofthe Resume command at this point is ignored. Another Erase Suspend command is written after the chip resumeserasing.
Do not issuing program command after entering erase-suspend-read mode.Fast Mode Set/Reset Command
Fast Mode function dispenses with the initial two unlock cycles required in the standard program commandsequence writing Fast Mode command into the command register. In this mode the required bus cycle forprogramming is two cycles instead of four bus cycles in standard program command. The read operation is alsoexecuted after exiting this mode. During the Fast mode, do not write any commands other than the Fast program/Fast mode reset command. To exit this mode, write Fast Mode Reset command into the command register.Refer to \"Embedded Program Algorithm for Fast Mode\". The VCC active current is required even CE = VIH duringFast Mode.
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Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded ProgramAlgorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). Refer to \"Em-bedded Program Algorithm for Fast Mode\".Extended Sector Group Protection
In addition to normal sector group protection, the device has Extended Sector Group Protection as extendedfunction. This function enables protection of the sector group by forcing VID on RESET pin and writes a commandsequence. Unlike conventional procedures, it is not necessary to force VID and control timing for control pins.The only RESET pin requires VID for sector group protection in this mode. The extended sector group protectionrequires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h)into the command register. Then the sector group addresses pins (A21, A20, A19, A18, and A17) and (A6, A3, A2, A1,A0) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (set VIL for the other addresses pins isrecommended), and write extended sector group protection command (60h). A sector group is typically protectedin 250 µs.
To verify programming of the protection circuitry, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14,A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set and write a command (40h). Following thecommand write, a logical “1” at device output DQ0 will produce for protected sector in the read operation. If theoutput data is logical “0”, write the extended sector group protection command (60h) again. To terminate theoperation, set RESET pin to VIH. (Refer to the “Extended Sector Group Protection Timing Diagram” in s SWITCH-ING WAVEFORMS and “Extended Sector Group Protection Algorithm” in s FLOW CHART.)Query Command (CFI : Common Flash Memory Interface)
To verify programming of the protection circuitry, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14,A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set and write a command (40h). Following thecommand write, a logical “1” at device output DQ0 will produce for protected sector in the read operation. If theoutput data is logical “0”, write the extended sector group protection command (60h) again. To terminate theoperation, set RESET pin to VIH. (Refer to the “Extended Sector Group Protection Timing Diagram” in s SWITCH-ING WAVEFORMS and “Extended Sector Group Protection Algorithm” in s FLOW CHART.)
The operation is initiated by writing the query command (98h) into the command register. Following the commandwrite, a read cycle from specific address retrives device information. Refer to \"Common Flash Memory InterfaceCode\" in s DEVICE BUS OPERATION in detail. Please note that output data of upper byte (DQ15 to DQ8) is “0”in word mode (16 bit) read. To terminate operation, write the Read/Reset command sequence into the register.HiddenROM ModeHiddenROM Region
The HiddenROM (HiddenROM) feature provides a Flash memory region that the system may access througha new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number(ESN) in the device with the ESN protected against modification. Once the HiddenROM region is protected, anyfurther modification of that region is impossible. This ensures the security of the ESN once the product is shippedto the field. This device occupies the address of the 000000h to 00007Fh.
After the system writes the HiddenROM Entry command sequence, it may read the HiddenROM region by usingdevice addresses A6 to A0 (A20 to A7 are all “0”). That is, the device sends only program command that wouldnormally be sent to the address to the HiddenROM region. This mode of operation continues until the systemissues the Exit HiddenROM command sequence, or until power is removed from the device. On power-up, orfollowing a hardware reset, the device reverts to sending commands to the address.
If you request Fujitsu to program the ESN in the device, please contact a Fujitsu representative for more infor-mation.
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HiddenROM Entry Command
The device has a HiddenROM area with One Time Protect function. This area is to enter the security code andto unable the change of the code once set. Program/erase is possible in this area until it is protected. Howeveronce it is protected, it is impossible to unprotect. Therefore extreme caution is required.
HiddenROM area is 128 words. This area is normally the “outermost” 8K words boot block area. Therefore, writethe HiddenROM entry command sequence to enter the HiddenROM area. It is called HiddenROM mode whenthe HiddenROM area appears.
Sectors other than the block area SA0 can be read during HiddenROM mode. Read/program of the HiddenROMarea is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit the Hidden-ROM mode. Note that any other commands should not be issued than the HiddenROM program/protection/resetcommands during the HiddenROM mode. When you issue the other commands including the suspend resumecapability, send the HiddenROM reset command first to exit the HiddenROM mode and then issue each com-mand.
HiddenROM Program Command
To program the data to the HiddenROM area, write the HiddenROM program command sequence during Hid-denROM mode. This command is the same as the program command in usual except to write the commandduring HiddenROM mode. Therefore the detection of completion method is the same as using the DQ7 datapolling, and DQ6 toggle bit. Need to pay attention to the address to be programmed. If the address other thanthe HiddenROM area is selected to program, data of the address are changed.During the write into the Hidden-ROM region, the program suspend command issuance is prohibited.HiddenROM Protect Command
The method to protect the HiddenROM is to apply high voltage (VID) to A9 and OE, set the sector address in theHiddenROM area and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and apply the write pulse during the HiddenROMmode. The same command sequence may be used because it is the same as the extension sector group protectin the past, except that it is in the HiddenROM mode and does not apply high voltage to the RESET pin. Pleaserefer to above mentioned “Extended Sector Group Protection” for details of sector group protect setting.The same command sequence may be used because it is the same as the extension sector group protect inthe past, except that it is in the HiddenROM mode and does not apply high voltage to the RESET pin. Pleaserefer to above mentioned “Extended Sector Group Protection” for details of sector group protect setting.Other sector will be effected if the address other than those for HiddenROM area is selected for the sectoraddress, so please be carefull. Once it is protected, protection can not be cancelled, so please pay the closestattention.
Write Operation StatusHardware Sequence Flags
Detailed in “Hardware Sequence Flags” are all the status flags which can determine the status of the bank forthe current mode operation. During sector erase, the part provides the status flags automatically to the I/O ports.The information on DQ2 is address-sensitive. This means that if an address from an erasing sector is consecu-tively read, the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector isconsecutively read. This allows users to determine which sectors are in erase and which are not.
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Hardware Sequence Flags Table
DQ6DQ7
DQ70DataData1DataDQ7DQ70DQ7DQ7DQ7N/A
ToggleToggleDataData1DataToggleToggleToggleToggleToggleToggleToggle
Status
Embedded Erase Algorithm
DQ500DataData0Data0111010
DQ301DataData0Data0010N/AN/AN/A
DQ21Toggle *1
DataDataToggle *1
Data1 *21N/AN/AN/AN/AN/A
DQ1 *3
0N/ADataDataN/ADataN/AN/AN/AN/A001
Embedded Program Algorithm
Program-Suspend-Read
Program (Program Suspend Sector) Suspend
Program-Supend -ReadMode
(Non-Program Suspended Sector)
Erase Suspend Read
(Erase Suspended Sector)
In
Progress
Erase
Erase Suspend Read
Suspend
(Non-Erase Suspended Sector)
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)Embedded Program Algorithm
ExceededEmbedded Erase AlgorithmTime Erase
Erase Suspend Program LimitsSuspend
(Non-Erase Suspended Sector)
ModeWrite to Buffer *4
BUSY State
Exceeded Timing LimitsABORT State
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle.*2 : Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit.*3 : DQ1 indicates the Write-to-Buffer ABORT status during Write-Buffer-Programming operations.
*4 : The Data Polling algorithm detailed in “Data Polling Algorithm” in “ s FLOW CHART” should be used for Write-Buffer-Programming operations. Note that DQ7 during Write-Buffer-Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.DQ7
Data PollingThe device features Data Polling as a method to indicate to the host that the Embedded Algorithms are inprogress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce acomplement of data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt toread the device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt toread the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm, anattempt to read device will produce a “1” on DQ7. The flowchart for Data Polling (DQ7) is shown in “Data PollingAlgorithm”. For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the fourwrite pulse sequences.
For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulsesequences.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the sixwrite pulse sequences. Data Polling must be performed at sector addresses of sectors being erased, not pro-tected sectors. Otherwise the status may become invalid.
If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, thenthat bank returns to the read mode. After an erase command sequence is written, if all sectors selected forerasing are protected, Data Polling on DQ7 is active for approximately 400 µs, then the bank returns to read mode.24
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Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may changeasynchronously while the output enable (OE) is asserted low. This means that device is driving status informationon DQ7 at one instant, and then that byte’s valid data at the next instant. Depending on when the system samplesthe DQ7 output, it may read the status or valid data. Even if device has completed the Embedded Algorithmoperation and DQ7 has a valid data, data outputs on DQ0 to DQ6 may still be invalid. The valid data on DQ0 toDQ7 will be read on successive read attempts.
The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithmor sector erase time-out. See “Toggle Bit Status” and “Data Polling during Embedded Algorithm Operation TimingDiagram”.DQ6
Toggle Bit I
The device also features the “Toggle Bit I” as a method to indicate to the host system that the EmbeddedAlgorithms are in progress or completed.
During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from thebusy bank will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithmcycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. Duringprogramming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulsesequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulsein the six write pulse sequences. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written is protected, the toggle bit will toggle for about 1 µs and then stoptoggling with data unchanged. In erase, the device will erase all selected sectors except for protected ones. Ifall selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back intoread mode, having data kept remained.
Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will causeDQ6 to toggle.
The system can use DQ6 to determine whether a sector is actively erased or is erase-suspended. When a bankis actively erased (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters theErase Suspend mode, DQ6 stops toggling. Successive read cycles during erase-suspend-program cause DQ6to toggle. See “AC Wavefrom for Toggle Bit I during Embedded Algorithm Operations”.DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Underthese conditions DQ5 will produce “1”. This is a failure condition indicating that the program or erase cycle wasnot successfully completed. Data Polling is only operating function of the device under this condition. The CEcircuit will partially power down device under these conditions (to approximately 2 mA) . The OE and WE pinswill control the output disable functions as described in \"MBM29PL65LM User Bus Operations Table (DW/W =VIL)\" and \"MBM29XL12DF User Bus Operations Table (DW/W = VIH)\" in s DEVICE BUS OPERATION.The DQ5 failure condition may also appear if a user tries to program a non-blank location without pre-erase. Inthis case the device locks out and never completes the Embedded Algorithm operation. Hence, the system neverreads valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used.If this occurs, reset device with the command sequence.DQ3
Sector Erase Timer
After completion of the initial sector erase command sequence, sector erase time-out begins. DQ3 will remainlow until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase commandsequence.
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If Data Polling or the Toggle Bit I indicates that a valid erase command has been written, DQ3 may be used todetermine whether the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erasecycle has begun. If DQ3 is low (“0”) , the device will accept additional sector erase commands. To insure thecommand has been accepted, the system software should check the status of DQ3 prior to and following eachsubsequent Sector Erase command. If DQ3 were high on the second status check, the command may not havebeen accepted.
See “Hardware Sequence Flags”.DQ2
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded EraseAlgorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If thedevice is in the erase-suspended-read mode, successive reads from the erase-suspended sector will causeDQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erasesuspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase SuspendProgram operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarizedas follows :
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.(DQ2 toggles while DQ6 does not.) See also “Toggle Bit Status” and \"DQ2 vs DQ6\".
Furthermore DQ2 can also be used to determine which sector is being erased. At the erase mode, DQ2 togglesif this bit is read from an erasing sector.Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a rowto determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bitafter the first read. After the second read, the system would compare the new value of the toggle bit with thefirst. If the toggle bit is not toggling, the device has completed the program or erase operation. The system canread array data on DQ7 to DQ0 on the following read cycle.
However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the systemalso should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should thendetermine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5went high. If the toggle bit is no longer toggling, the device has successfully completed the program or eraseoperation. If it is still toggling, the device did not complete the operation successfully, and the system must writethe reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has notgone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, deter-mining the status as described in the previous paragraph. Alternatively, it may choose to perform other systemtasks. In this case, the system must start at the beginning of the algorithm when it returns to determine thestatus of the operation. Refer to “Toggle Bit Algorithm”.
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Toggle Bit Status TableDQ7DQ701DQ7
Mode
ProgramErase
Erase-Suspend-Read
(Erase-Suspended Sector) Erase-Suspend-Program
DQ6ToggleToggle1Toggle
DQ21Toggle *1Toggle *1
1 *2
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. *2 : Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit.DQ1
Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a \"1\".The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading arraydata. See \"Write Buffer Programming Operations\" section for more details.Data Protection
The device is designed to offer protection against accidental erasure or programming caused by spurious systemlevel signals that may exist during power transitions. During power up device automatically resets internal statemachine to Read mode. Also, with its control register architecture, alteration of memory contents only occursafter successful completion of specific multi-bus cycle command sequence.
Device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up andpower-down transitions or system noise.Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC lessthan VLKO. If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled.Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the VCC levelis greater than VLKO. It is the user’s responsibility to ensure that the control pins are logically correct to preventunintentional writes when VCC is above VLKO.
If Embedded Erase Algorithm is interrupted, the intervened erasing sector(s) is(are) not valid.Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle, CE and WEmust be a logical zero while OE is a logical one.Power-up Write Inhibit
Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.The internal state machine is automatically reset to read mode on power-up.Sector Protection
Device user is able to protect each sector group individually to store and protect data. Protection circuit voidsboth write and erase commands that are addressed to protected sectors. Any commands to write or eraseaddressed to protected sector are ignored.
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sABSOLUTE MAXIMUM RATINGS
Parameter
Storage Temperature
Ambient Temperature with Power AppliedVoltage with Respect to Ground All Pins Except A9, OE, and RESET *1,*2Power Supply Voltage *1A9, OE, and RESET *1,*3WP/ACC *1,*3
*1 : Voltage is defined on the basis of VSS = GND = 0 V.
*2 : Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot
VSS to –0.2 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V.During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns*3 : Minimum DC input voltage is –0.5V. During voltage transitions, these pins may undershoot VSS to –0.2 V
for periods of up to 20 ns.Voltage difference between input and supply voltage ( VIN–VCC) dose not
exceed to +9.0 V.Maximum DC input voltage is +12.5 V which may overshoot to +14.0 V for periods of up to 20 ns .WARNING:Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
SymbolTstgTAVIN, VOUTVCC,VCCQ
VINVACC
RatingMin–55–20–0.5–0.5–0.5–0.5
Max+125+85VCC +0.5+4.0+12.5+12.5
Unit°C°CVVVV
sRECOMMENDED OPERATING RANGES*1
Parameter
Ambient TemperatureVCC Supply Voltage *2, *3VCCQ Supply Voltage *2, *3
9010
SymbolTAVCCVCCQ
Value
Min–20–20+3.0
VCC
Max+70+85+3.6
Unit°CVV
*1 : Operating ranges define those limits between which the functionality of the device is guaranteed.*2 : Voltage is defined on the basis of VSS = GND = 0 V.*3 : VCC and VCCQ supply voltage must be on the same level.
WARNING:The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device isoperated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operationoutside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented onthe data sheet. Users considering application outside the listed conditions are advised to contact theirFUJITSU representatives beforehand.
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sMAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
1.Maximum Undershoot Waveform+0.6 V–0.5 V–2.0 V20 ns20 ns20 ns2.Maximum Overshoot Waveform 1 20 nsVCC +2.0 VVCC +0.5 V0.7 × VCC20 ns20 ns3.Maximum Overshoot Waveform 2
20 ns
+14.0 V+12.5 VVCC +0.5 V
20 ns
20 ns
Note : This waveform is applied for A9, OE and RESET.29
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sELECTRICAL CHARACTERISTICS
1.DC Characteristics
Parameter
Input Leakage CurrentOutput Leakage CurrentA9, OE, RESET Inputs Leakage CurrentVCC Active Current (Read ) *1,*2
VCC Active Current (Intra-Page Read ) *2 VCC Active Current (Program / Erase) *2,*3VCC Standby Current *VCC Reset Current *2
VCC Automatic Sleep Current *4
VCC Active Current
(Erase-Suspend-Program) *2ACC Accelerated Program CurrentInput Low LevelInput High Level
Voltage for ACC Sector
Protection/Unprotection and Program Acceleration
Voltage for Autoselect, andTemporary Sector UnprotectedOutput Low Voltage LevelOutput High Voltage LevelLow VCC Lock-Out Voltage
2
Sym-bolILIILOILITICC1ICC2ICC3ICC4ICC5ICC6ICC7
Conditions
VIN = VSS to VCC, VCC = VCC Max
VCC = VCC Max,
A9, OE, RESET = 12.5 VCE = VIL, OE = VIH, f = 5 MHzCE = VIL, OE = VIH, f = 10 MHz CE = VIL, OE = VIH, tPRC = 25 ns, 4-Word
CE = VIL, OE = VIH
CE = VCC ± 0.3 V, RESET = VCC ± 0.3 V,
OE = VIH, WP = VCC ± 0.3 VRESET = VCC ± 0.3 V,WP = VCC ± 0.3 V
CE = VSS ± 0.3 V, RESET = VCC ± 0.3 V,VIN = VCC ± 0.3 V or Vss ± 0.3 V, WP = VCC ± 0.3 VCE = VIL, OE = VIHCE = VIL, OE = VIH,Vcc = Vcc Max,ACC =VACC Max
——
ACC PinVcc PinWP PinOthers
Value
Min–2.0–1.0–1.0———————————–0.50.7 × VCC
11.511.5—0.85 × VCCQ
2.3
Typ————1535105011150————12.012.0———
Max+2.0+1.0+1.035255020605556045600.6VCC + 0.312.512.50.45—2.5
UnitµAµAµAmAmAmAmAµAµAµAmA
VOUT = VSS to VCC, VCC = VCC Max
IACCVILVIH
mAVVVVVVV
VACCVCC = 3.0 V to 3.6 VVIDVOLVOHVLKO
VCC = 3.0 V to 3.6 VIOL = 4.0 mA, VCC = VCC Min,VCCQ = VCCQ Min
IOH = –2.0 mA, VCC = VCC Min,VCCQ = VCCQ Min
—
*1 : The lCC current listed includes both the DC operating current and the frequency dependent component.*2 : Maximum ICC values are tested with VCC = VCC Max and VCCQ = VCCQ Max.
*3 : ICC active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress.*4 : Automatic sleep mode enables the low power mode when address remain stable for tACC + 30 ns. 30
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2.AC Characteristics
•Read Only Operations Characteristics
Parameter
Read Cycle TimeAddress to Output DelayChip Enable to Output DelayPage Read Cycle TimePage Address to Output DelayOutput Enable to Output DelayChip Enable to Output High-ZOutput Enable Hold Time
ReadToggle and Data PollingtOEHtDFtOHtREADY
tOEHtDFtOHtREADY
Symbol
JEDEC
Standard
Condi-tion—CE = VIL,OE = VILOE = VIL
—CE = VIL, OE = VIL
———————
MBM29PL65LM-90*MBM29PL65LM-10*
Min90——25———010—0—
Typ————————————
Max—9090—252525——25—20
Min100——30———010—0—
Typ————————————
Max—100100—303030——30—20
Unitnsnsnsnsnsnsnsnsnsnsnsµs
tRCtACCtCEtPRCtPACCtOEtDF
tRCtACCtCEtPRCtPACCtOEtDF
Output Enable to Output High-ZOutput Hold Time From Addresses, CE or OE, Whichever Occurs FirstRESET Pin Low to Read Mode* : Test Conditions;
Input pulse levels : 0.0 V / VCCInput rise times : 5 nsInput fall times : 5 ns
Timing measurement reference level
Input : 0.5 × VCCOutput : 0.5 × VCC
Output Load : 1 TTL + 30 pF
•Test Conditions3.3 VDiode = 1N30or Equivalent2.7 kΩDeviceUnderTest6.2 kΩCLDiode = 1N30or Equivalent31
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•Write (Erase/Program) Operations
Parameter
Write Cycle TimeAddress Setup Time
Address Setup Time to OE Low During Toggle Bit PollingAddress Hold Time
Address Hold Time from CE or OE High During Toggle Bit PollingData Setup TimeData Hold Time
Output Enable Setup TimeCE High During Toggle Bit PollingOE High During Toggle Bit PollingRead Recover Time Before Write (OE High to WE Low) Read Recover Time Before Write (OE High to CE Low) CE Setup TimeWE Setup TimeCE Hold TimeWE Hold TimeCE Pulse WidthWrite Pulse WidthCE Pulse Width HighWrite Pulse Width High
Symbol
JEDECStandard
MBM29PL65LM-90MBM29PL65LM-10Min900154503500202000000035352530——
Typ————————————————————23.51001.0—
Max————————————————————————
Min1000154503500202000000035352530———50
Typ————————————————————23.51001.0—
Max————————————————————————
Unitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsµsµssµs
tWCtAStASOtAHtAHTtDStDHtOEStCEPHtOEPHtGHWLtGHELtCStWStCHtWHtCPtWPtCPHtWPH
tWCtAStASOtAHtAHTtDStDHtOEStCEPHtOEPHtGHWLtGHELtCStWStCHtWHtCPtWPtCPHtWPHtWHWH1tWHWH2tVCS
Effective Page Programming Time
Per Word
(Write Buffer Programming) tWHWH1Programming TimeSector Erase Operation *1VCC Setup Time
Word
tWHWH2tVCS
—50
(Continued)32
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(Continued)Parameter
Rise Time to VID *2Rise Time to VACC *3
Voltage Transition Time *2Write Pulse Width *2
OE Setup Time to WE Active *2CE Setup Time to WE Active *2RESET Pulse WidthRESET High Time Before ReadDelay Time from Embedded Output Enable
Erase Time-out Time
Erase Suspend Transition Time
Symbol
JEDEC
Standard
MBM29PL65LM-90Min500500410044500100—50—
Typ———————————
Max————————90—20
MBM29PL65LM-10Min500500410044500100—50—
Typ———————————
Max————————100—20
Unitnsnsµsµsµsµsnsnsnsµsµs
tVIDRtVACCRtVLHTtWPPtOESPtCSPtRPtRHtEOEtTOWtSPD
tVIDRtVACCRtVLHTtWPPtOESPtCSPtRPtRHtEOEtTOWtSPD
*1 : This does not include the preprogramming time.*2 : This timing is for Sector Group Protection operation.*3 : This timing is for Accelerated Program operation.
sERASE AND PROGRAMMING PERFORMANCE
Parameter
Sector Erase TimeProgramming Time
Effective Page Programming Time(Write Buffer Programming)Chip Programming TimeAbsolute Maximum
Programming Time (16 words)Erase/Program Cycle
Limits
Min—————100,000
Typ 110023.5———
Max153000—6006—
Unitsµsµssmscycle
Non programming within the same page
—
Excludes system-level overhead
Remarks
Excludes programming time prior to erasure
sTSOP (1) PIN CAPACITANCE
Parameter
Input CapacitanceOutput CapacitanceControl Pin CapacitanceRESET pin and ACC Pin Capacitance
SymbolCINCOUTCIN2CIN3
Test SetupVIN = 0VOUT = 0VIN = 0VIN = 0
Value
Min————
Typ88.5820
Max10121025
UnitpFpFpFpF
Note : Test conditions TA = +25°C, f = 1.0 MHz
DQ15 pin capacitance is stipulated by output capacitance.
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sTIMING DIAGRAM
•Key to Switching Waveforms
WAVEFORMINPUTSMust BeSteadyMayChangefrom H to LMayChangefrom L to H“H” or “L”Any ChangePermittedDoes NotApplyOUTPUTSWill BeSteadyWill BeChangingfrom H to LWill BeChangingfrom L to HChangingStateUnknownCenter Line isHigh-Impedance“Off” State (1) Read Operation Timing DiagramtRCAddressAddress StabletACCCEtOEtDFOEtOEHWE tCEtOHDataHigh-ZOutput ValidHigh-Z34
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(2) Page Read Operation Timing Diagram A21 to A2A1, A0Address ValidAatRCtACCAbtPRCAcCEtCEOEtOEHtOEtDFWEDataHigh-ZDatPACCtOHtPACCtOHDbtOHDc (3) Hardware Reset Timing DiagramtRCAddresstACCAddress StableCEtRHtRPtRHtCERESETtOHDataHigh-ZOutput Valid 35
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(4) Alternate WE Controlled Program Operation Timing Diagram3rd Bus CycleAddress555htWCtASPAtAHData PollingPAtRCCEtCStCHtCEOEtGHWLtWPtWPHtWHWH1tOEWEtDStDHtDFtOHDataA0hPDDQ7DOUTDOUTPAPDDQ7DOUT : Address of the memory location to be programmed. : Data to be programmed at word address. : The output of the complement of the data written to the device. : The output of the data written to the deviceNote : Figure indicates the last two bus cycles out of four bus cycle sequence.36
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(5) Alternate CE Controlled Program Operation Timing Diagram3rd Bus CycleData PollingPA ASAddress555htWCtPAtAHWEtWStWHOEtGHELtCPtCPHtWHWH1CEtDStDHData A0hPDDQ 7D OUTPAPDDQ7DOUT : Address of the memory location to be programmed. : Data to be programmed at word address. : The output of the complement of the data written to the device. : The output of the data written to the device.Note : Figure indicates the last two bus cycles out of four bus cycle sequence.37
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(6) Chip/Sector Erase Operation Timing DiagramAddress555htWC2AAhtAStAH555h555h2AAhSA*SA*CEtCStCHOEtGHWLtWPtWPHtTOWWEtDSAAhtDH55h80hAAh55h10h for Chip Erase10h/30htBUSY30hDataRY/BYtVCSVCC* : SA is the sector address for Sector Erase. Address = 555h (Word), AAAh (Byte) for Chip Erase.38
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(7) Erase Suspend Operation Timing DiagramAddressXXXhtWCCEtCStWPtCHWEtDSB0htSPDDataRY/BY (8) Data Polling during Embedded Algorithm Operation Timing Diagram AddressVACEtDFtCHtOEOEtOEHWE4 mstCE*DQ7DataDQ7DQ7 =Valid DataHigh-ZtWHWH1 or 2DQ6 to DQ0DataDQ6 to DQ0 =Output FlagtEOEDQ6 to DQ0Valid DataHigh-Z* : DQ7 = Valid Data (The device has completed the Embedded operation.)Note : When checking Hardware Sequence Flags during program operations, it should be checked 4 µs after issuing program command.39
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(9) Toggle Bit l Timing Diagram during Embedded Algorithm Operations AddresstAHTtASOtAHTtASCEtCEPHWE4 mstOEPHtOEHOEtDHtOEtCEDQ 6/DQ2DataToggleDataToggleDataToggleData*TogglingStopOutputValid* : DQ6 stops toggling (The device has completed the Embedded operation).Note : When checking Hardware Sequence Flags during program operations, it should be checked 4 µs after issuing program command. (10) DQ2 vs. DQ6
EnterEmbeddedErasingWEEraseSuspendEraseEnter EraseSuspend ProgramEraseSuspendProgramEraseResumeErase SuspendReadEraseEraseCompleteErase SuspendReadDQ6
DQ2*
ToggleDQ2 and DQ6 with OE or CE* : DQ2 is read from the erase-suspended sector.
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(11) RESET Timing Diagram ( Not during Embedded Algorithms )CE, OEtRHRESETtRPtREADY (12) RESET Timing Diagram ( During Embedded Algorithms )tREADYCE, OERESETtRP41
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(13) Sector Group Protection Timing DiagramA21, A20, A19 A18, A17SGAXSGAYA6, A3, A2, A0A1VIDVIHA9VIDVIHOEtVLHTtWPPtVLHTtVLHTtVLHTWEtOESPCEtCSPDatatVCStOE01hVCCSGAX : Sector Group Address to be protectedSGAY : Next Sector Group Address to be protected42
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(14) Temporary Sector Group Unprotection Timing DiagramVCCtvCStVIDRtVLHTVIDRESETVSS, VIL or VIHCEWEtVLHTProgram or Erase Command SequencetVLHTUnprotection period43
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(15) Extended Sector Group Protection Timing DiagramVCCtVCSRESETtVLHTtVIDRAddressSGAXSGAXSGAYA6, A3, A2, A0A1CEOETIME-OUTWEData60h60h40htOE01h60hSGAXSGAY : Sector Group Address to be protected : Next Sector Group Address to be protectedTIME-OUT : Time-Out window = 250 ms (Min) 44
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(16) Accelerated Program Timing DiagramVCCtVCSVACCACCtVACCRtVLHTCEWEtVLHT Program Command SequencetVLHTAcceleration period45
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sFLOW CHART
(1) Embedded ProgramTM AlgorithmEMBEDDED ALGORITHMSStartWrite ProgramCommand Sequence(See Below)Data PollingEmbeddedProgramAlgorithmin progressNoVerify Data?YesLast Address?YesIncrement AddressNoProgramming CompletedProgram Command Sequence (Address/Command):555h/AAh2AAh/55h555h/A0hProgram Address/Program Data46
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(2) Embedded EraseTM AlgorithmEMBEDDED ALGORITHMSStartWrite EraseCommand Sequence(See Below)Data PollingEmbeddedEraseAlgorithmin progressNoData = FFh?YesErasure CompletedChip Erase Command Sequence(Address/Command):555h/AAhIndividual Sector/Multiple Sector Erase Command Sequence(Address/Command):555h/AAh2AAh/55h2AAh/55h555h/80h555h/80h555h/AAh555h/AAh2AAh/55h2AAh/55hSector Address/30hSector Address/30hSector Address/30h555h/10hAdditional sectorerase commandsare optional.47
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(3) Data Polling AlgorithmStartWait 4 ms afterissuing ProgramcommandRead Byte(DQ 7 to DQ 0)Addr. = VADQ 7 = Data?NoNoDQ 5 = 1?YesRead Byte(DQ 7 to DQ 0)Addr. = VAYesDQ 7 = Data? *NoFailYesPassVA = Valid address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple sectorerases operation = Any of the sector addresses within the sector not being protected during chip erase operation (There may not be accurate indications to determine that the data polling has been completed.) * : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.48
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(4) Toggle Bit AlgorithmStartWait 4 s afterissuing ProgramcommandRead DQ7 to DQ0Addr. = \"H\" or \"L\"*1Read DQ7 to DQ0Addr. = \"H\" or \"L\"DQ6= Toggle?YesNoNoDQ5 = 1?Yes*1, *2Read DQ7 to DQ0Addr. = \"H\" or \"L\"*1, *2Read DQ7 to DQ0Addr. = \"H\" or \"L\"DQ6 = Toggle?YesProgram/EraseOperation NotComplete.WriteReset CommandNoProgram/EraseOperationComplete*1 : Read Toggle bit twice to determine whether it is toggling.*2 : Recheck Toggle bit because it may stop toggling as DQ5 changes to “1”.49
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(5) Sector Group Protection AlgorithmStartSetup Sector Group Addr.(A21, A20, A19, A18, A17)PLSCNT = 1OE = VID, A9 = VIDCE = VIL, RESET = VIHA6 = A3 = A2 = A0 = VIL, A1 = VIHActivate WE PulseIncrement PLSCNTTime out 100 µsWE = VIH, CE = OE = VIL(A9 should remain VID)Read from Sector GroupAddr. = SGA, A1 = VIHA6 = A3 = A2 = A0 = VIL(NoPLSCNT = 25?YesRemove VID from A9Write Reset CommandNo)Data = 01h?YesProtect Another SectorGroup?NoYesDevice FailedRemove VID from A9Write Reset CommandSector Group ProtectionCompleted50
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(6) Temporary Sector Group Unprotection AlgorithmStartRESET = VID *1Perform Erase orProgram OperationsRESET = VIHTemporary Sector GroupUnprotection Completed*2*1 : All protected sector groups are unprotected.*2 : All previously protected sector groups are protected.51
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MBM29PL65LM-90/10
(7) Extended Sector Group Protection AlgorithmStartRESET = VIDWait to 4 µsDevice is Operating inTemporary Sector GroupUnprotection ModeNoExtended Sector GroupProtection Entry?YesTo Setup Sector Group Protection Write XXXh/60h PLSCNT = 1To Protect Sector GroupWrite 60h to Sector Address(A6 = A3 = A2 = A0 =VIL, A1 = VIH)Increment PLSCNTTime Out 250 µsSetup Next Sector GroupAddressTo Verify Sector Group ProtectionWrite 40h to Sector Address(A6 = A3 = A2 = A0 =VIL, A1 = VIH)Read from Sector GroupAddress(A6 = A3 = A2 = A0 =VIL, A1 = VIH)NoNoPLSCNT = 25?YesRemove VID from RESETWrite Reset CommandData = 01h?Yes Protection Other SectorGroup ?NoDevice FailedRemove VID from RESETWrite Reset CommandYesSector Group ProtectionCompleted52
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MBM29PL65LM-90/10
(8) Embedded ProgramTM Algorithm for Fast ModeFAST MODE ALGORITHMStart555h/AAh2AAh/55hSet Fast Mode555h/20hXXXh/A0hProgram Address/Program DataData PollingVerify Data?YesNoLast Address?YesProgramming CompletedNoIn Fast ProgramIncrement AddressXXXh/90hReset Fast ModeXXXh/F0hNote : The sequence is applied for Word ( ×16 ) mode.53
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MBM29PL65LM-90/10
sORDERING INFORMATION
Part No.
MBM29PL65LM90TNMBM29PL65LM10TN
MBM29PL65LM
90 TN
PACKAGE TYPE
TN=48-Pin Thin Small Outline Package
(TSOP(1)) Standard Pinout
Package
48-pin, plastic TSOP (1)
(FPT-48P-M19) (Normal Bend)
Access Time (ns)
90 ns100 ns
Remarks
SPEED OPTION
90 = 90 ns access time10 = 100 ns access time
DEVICE NUMBER/DESCRIPTION Mega-bit (8M × 16)
3.0 V-only Page Mode MirrorFlash
54
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MBM29PL65LM-90/10
sPACKAGE DIMENSION
48-pin plastic TSOP(1)(FPT-48P-M19)Note 1) * : Values do not include resin protrusion.Resin protrusion and gate protrusion are +0.15(.006)Max(each side).Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.LEAD No.148INDEXDetails of \"A\" part0.25(.010)0~8˚0.60±0.15(.024±.006)242520.00±0.20(.787±.008)*18.40±0.20(.724±.008)*12.00±0.20(.472±.008)1.10–0.05+0.10+.004.043–.002(Mountingheight)0.50(.020)\"A\"0.10(.004)0.17–0.08.007C+0.03+.001–.0030.10±0.05(.004±.002)(Stand off height)0.22±0.05(.009±.002)0.10(.004)M2003 FUJITSU LIMITED F48029S-c-6-7Dimensions in mm (inches)Note : The values in parentheses are reference values.55
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MBM29PL65LM-90/10
FUJITSU LIMITED
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