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专利名称：CMOS I/O circuit with 3.3 volt output and
tolerance of 5 volt input
发明人：Hung-jen Liao申请号：US08/518700申请日：19950824公开号：US05546019A公开日：19960813
摘要：As VLSI chip design migrates from 5 volt designs to lower voltage designs, suchas 3.3 volts, interfacing components with different power supplies is an unavoidable issue.This invention provides simple and inexpensive circuits which provide full rail to rail outputvoltage swing and prevent the PN junctions in the isolation wells of metal oxidesemiconductor field effect transistors from becoming forward biased. This preventsexcessive leakage currents and component damage which can occur when PN junctions inthe isolation wells of PMOS field effect transistors become forward biased.
申请人：TAIWAN SEMICONDUCTOR MANUFACTURE COMPANY
代理人：George O. Saile,Larry J. Prescott
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