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专利名称：INSTRUCTION SET ARCHITECTURE WITH
DECOMPOSING OPERANDS
发明人：Tobias Gemmeke,Markus Kaltenbach,Nicolas
Maeding
申请号：US12366169申请日：20090205
公开号：US20100199074A1公开日：20100805
专利附图：
摘要：Instead of having a processor with an instruction set architecture (ISA) thatincludes fixed architected operands, an improved processor supports additional
characteristic bits for computing instructions (e.g., a multiply-add, load/store
instructions). Such additional bits for the certain instructions influence the processing ofthese instructions by the processor. Also, a new instruction is introduced for furtherusage of the proposed method. Typically these additional characteristic bits as well asthe instruction can be automatically generated by compilers to provide relatively well-suited instruction sequences for the processor.
申请人：Tobias Gemmeke,Markus Kaltenbach,Nicolas Maeding
地址：Stutensee DE,Leinfelden DE,Holzgerlingen DE
国籍：DE,DE,DE
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